Datasheet

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SN54ALVTH16373, SN74ALVTH16373

2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCES067F – JUNE 1996 – REVISED JANUARY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

State-of-the-Art Advanced BiCMOS

Technology (ABT)

Widebus

 Design for

2.5-V and 3.3-V Operation and Low Static

Power Dissipation

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 2.3-V to

3.6-V V

)

Typical V

OLP

(Output Ground Bounce)

< 0.8 V at V

= 3.3 V, T

= 25°C

High Drive (–24/24 mA at 2.5-V and

–32/64 mA at 3.3-V V

)

Power Off Disables Outputs, Permitting

Live Insertion

High-Impedance State During Power Up

and Power Down Prevents Driver Conflict

Uses Bus Hold on Data Inputs in Place of

External Pullup/Pulldown Resistors to

Prevent the Bus From Floating

Auto3-State Eliminates Bus Current

Loading When Output Exceeds V

+ 0.5 V

Latch-Up Performance Exceeds 250 mA Per

JESD 17

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model; and Exceeds 1000 V

Using Charged-Device Model, Robotic

Method

Flow-Through Architecture Facilitates

Printed Circuit Board Layout

Distributed V

and GND Pin Configuration

Minimizes High-Speed Switching Noise

Package Options Include Plastic Shrink

Small-Outline (DL), Thin Shrink

Small-Outline (DGG), Thin Very

Small-Outline (DGV) Packages, and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

description

The ’ALVTH16373 devices are 16-bit transparent D-type latches with 3-state outputs designed for 2.5-V or 3.3-V

operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices

are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working

registers.

These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,

the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up

at the D inputs.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

SN54ALVTH16373 . . . WD PACKAGE

SN74ALVTH16373 ... DGG, DGV, OR DL PACKAGE

(TOP VIEW)

1OE

1Q1

1Q2

GND

1Q3

1Q4

1Q5

1Q6

GND

1Q7

1Q8

2Q1

2Q2

GND

2Q3

2Q4

2Q5

2Q6

GND

2Q7

2Q8

2OE

1LE

1D1

1D2

GND

1D3

1D4

1D5

1D6

GND

1D7

1D8

2D1

2D2

GND

2D3

2D4

2D5

2D6

GND

2D7

2D8

2LE

Summary of content (18 pages)

PAGE 1
SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F – JUNE 1996 – REVISED JANUARY 1999 D D D D D D D D D D D D D State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus  Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C High Drive (–24/24 mA at 2.
PAGE 2
SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F – JUNE 1996 – REVISED JANUARY 1999 description (continued) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
PAGE 3
SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F – JUNE 1996 – REVISED JANUARY 1999 logic diagram (positive logic) 1OE 1LE 1D1 1 2OE 48 2LE C1 47 2 1D 1Q1 24 25 C1 2D1 36 13 1D 2Q1 To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F – JUNE 1996 – REVISED JANUARY 1999 recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 3) SN54ALVTH16373 SN74ALVTH16373 MIN MAX MIN 3.6 3 VCC VIH Supply voltage 3 High-level input voltage 2 VIL VI Low-level input voltage IOH High-level output current IOL ∆t/∆v TYP TYP 3.6 2 0 5.5 0.8 0 V VCC V 5.
PAGE 5
SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F – JUNE 1996 – REVISED JANUARY 1999 electrical characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER VIK VOH VCC = 2.3 V, VCC = 2.3 V to 2.7 V, II = –18 mA IOH = –100 µA 3V VCC = 2 2.3 IOH = –6 mA IOH = –8 mA VCC = 2.3 V to 2.7 V, VOL VCC = 2 2.3 3V Control inputs VCC = 2.7 V, VCC = 0 or 2.
PAGE 6
SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F – JUNE 1996 – REVISED JANUARY 1999 electrical characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER VIK VOH VCC = 3 V, VCC = 3 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 3 V IOH = –24 mA IOH = –32 mA VCC = 3 V to 3.6 V, VOL VCC = 3 V Control inputs Ioff IBHL‡ IBHH§ IBHLO¶ IBHHO# IEX|| 2 IOL = 100 µA IOL = 16 mA 0.
PAGE 7
SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F – JUNE 1996 – REVISED JANUARY 1999 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) SN54ALVTH16373 MIN tw Pulse duration, LE high tsu Setup time, time data before LE↓ th Hold time, time data after LE↓ MAX SN74ALVTH16373 MIN 1.5 1.5 Data high 1.1 1 Data low 1.6 1.5 1 0.9 1.6 1.
PAGE 8
SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F – JUNE 1996 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 9
SN54ALVTH16373, SN74ALVTH16373 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCES067F – JUNE 1996 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 3V 3V Timing Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 3V 1.5 V 3V 1.5 V 0V 0V Output Output Waveform 1 S1 at 6 V (see Note B) 3V 1.5 V 1.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ALVTH16373DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 SN74ALVTH16373GR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN74ALVTH16373VR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVTH16373DLR SSOP DL 48 1000 367.0 367.0 55.0 SN74ALVTH16373GR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74ALVTH16373VR TVSOP DGV 48 2000 367.0 367.0 38.
PAGE 14
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 15
PAGE 16
PAGE 17
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 18
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