Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Register, Bidirectional Push pull SOIC 16 N

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SDAS212A − DECEMBER 1983 − REVISED DECEMBER 1994

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

• Parallel-to-Serial, Serial-to-Parallel

Conversions

• Left or Right Shifts

• Parallel Synchronous Loading

• Direct Overriding Clear

• Temporary Data-Latching Capability

• Package Options Include Plastic

Small-Outline Packages (D), Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

description

These 4-bit bidirectional universal shift registers

feature parallel outputs, right-shift and left-shift

serial (SR SER, SL SER) inputs, operating-

mode-control (S0, S1) inputs, and a direct

overriding clear (CLR

) line. The registers have

four distinct modes of operation:

• Inhibit clock (temporary data latch/do nothing)

• Shift right (in the direction Q

toward Q

)

• Shift left (in the direction Q

toward Q

)

• Parallel (broadside) load

Parallel synchronous loading is accomplished by

applying the four bits of data and taking both S0

and S1 high. The data is loaded into the

associated flip-flops and appears at the outputs

after the positive transition of the clock (CLK)

input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low.

Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left

synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when

both mode-control inputs are low.

The SN54AS194 is characterized for operation over the full military temperature range of −55°C to 125°C. The

SN74AS194 is characterized for operation from 0°C to 70°C.

CLR

SR SER

SL SER

GND

CLK

SN54AS194 ...J PACKAGE

SN74AS194 ...D OR N PACKAGE

(TOP VIEW)

3212019

910111213

CLK

SR SER

CLR

SL SER

GND

NC − No internal connection

SN54AS194 ...FK PACKAGE

(TOP VIEW)

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Summary of content (18 pages)

PAGE 1
SDAS212A − DECEMBER 1983 − REVISED DECEMBER 1994 • • • • • • SN54AS194 . . . J PACKAGE SN74AS194 . . .
PAGE 2
SDAS212A − DECEMBER 1983 − REVISED DECEMBER 1994 FUNCTION TABLE INPUTS MODE CLR OUTPUTS SERIAL S1 S0 CLK PARALLEL LEFT RIGHT A B C D QA QB QC QD L X X X X X X X X X L L L L H X X L X X X X X X QA0 QB0 QC0 QD0 H H H ↑ X X a b c d a b c d H L H ↑ X H X X X X H QAn QBn QCn H L H ↑ X L X X X X L H L ↑ H X X X X X QBn QAn QCn QBn QDn QCn H H H L
PAGE 3
SDAS212A − DECEMBER 1983 − REVISED DECEMBER 1994 logic diagram (positive logic) Parallel Inputs A S1 S0 SR SER 10 D 6 3 9 2 7 Two Identical Channels Not Shown† 1S CLK CLR SL SER 1S C1 1R C1 1R R R 11 1 15 12 QA QD Parallel Outputs † I/O ports not shown: QB (14) and QC (13) Pin numbers shown are for the D, J, and N packages.
PAGE 4
SDAS212A − DECEMBER 1983 − REVISED DECEMBER 1994 CLK ModeControl Inputs S0 S1 CLR Serial Data Inputs Parallel Data Inputs R L A H B L C H D L QA QB Outputs QC QD Shift Right Shift Left Inhibit Clear Clear Load Figure 1. Typical Clear, Load, Right-Shift, and Clear Sequences absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . .
PAGE 5
SDAS212A − DECEMBER 1983 − REVISED DECEMBER 1994 recommended operating conditions SN54AS194 SN74AS194 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current −2 −2 mA IOL fclock* Low-level output current 20 20 mA 80 MHz tw* tsu* High-level input voltage 2 Clock frequency 0 4.
PAGE 6
SDAS212A − DECEMBER 1983 − REVISED DECEMBER 1994 switching characteristics (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† SN54AS194 MIN fmax* tPLH tPHL tPHL MAX 75 CLK Any Q CLR Any Q UNIT SN74AS194 MIN MAX 80 MHz 2.5 8 3 7 2.5 8 3 7 3.
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SDAS212A − DECEMBER 1983 − REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (3) 28-Apr-2011 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74AS194DR Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.5 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AS194DR SOIC D 16 2500 333.2 345.9 28.
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