Datasheet

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SDAS038C − DECEMBER 1982 − REVISED DECEMBER 1994
Copyright  1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
• Generate Either Odd or Even Parity for Nine
Data Lines
• Cascadable for n-Bit Parity
• Can Be Used to Upgrade Existing Systems
Using MSI Parity Circuits
• Package Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
description
These universal 9-bit parity generators/checkers
utilize advanced Schottky high-performance
circuitry and feature odd (Σ ODD) and even (Σ EVEN) outputs to facilitate operation of either odd- or even-parity
applications. The word-length capability is easily expanded by cascading.
These devices can be used to upgrade the performance of most systems utilizing the SN74ALS180 and
SN74AS180 parity generators/checkers. Although the SN74ALS280 and SN74AS280 are implemented without
expander inputs, the corresponding function is provided by the availability of an input (I) at terminal 4 and the
absence of any internal connection at terminal 3. This permits the SN74ALS280 and SN74AS280 to be
substituted for the SN74ALS180 and SN74AS180 in existing designs to produce an identical function even if
the devices are mixed with existing SN74ALS180 and SN74AS180 devices.
All SN74AS280 inputs are buffered to lower the drive requirements.
The SN74ALS280 and SN74AS280 are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
NO. OF INPUTS
A−I
OUTPUTS
A−I
THAT ARE HIGH
Σ EVEN Σ ODD
0, 2, 4, 6, 8 H L
1, 3, 5, 7, 9 L H
logic symbol
†
2k
12
E
8
A
9
B
10
C
11
D
13
F
1
G
2
H
4
I
6
5
Σ EVEN
Σ ODD
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
G
H
NC
I
Σ EVEN
Σ ODD
GND
V
CC
F
E
D
C
B
A
NC − No internal connection
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