Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74AS PDIP 20

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

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SDAS022C − DECEMBER 1982 − REVISED JANUARY 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

• High Capacitive-Drive Capability

• ′ALS804A Has Typical Delay Time of 4 ns

= 50 pF) and Typical Power Dissipation

of 3.4 mW Per Gate

• ′AS804B Has Typical Delay Time of 2.6 ns

= 50 pF) and Typical Power Dissipation

of Less Than 9 mW Per Gate

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Plastic (N)

and Ceramic (J) 300-mil DIPs

description

These devices contain six independent 2-input

NAND drivers. They perform the Boolean

functions Y = A

• B or Y = A + B in positive logic.

The SN54ALS804A and SN54AS804B are

characterized for operation over the full military

temperature range of −55°C to 125°C. The

SN74ALS804A and SN74AS804B are

characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each driver)

INPUTS

OUTPUT

A B

OUTPUT

H H L

L XH

X L H

logic symbol

†

logic diagram (positive logic)

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

GND

SN54ALS804A, SN54AS804B...J PACKAGE

SN74ALS804A, SN74AS804B...DW OR N PACKAGE

(TOP VIEW)

3 2 1 20 19

910111213

SN54ALS804A, SN54AS804B...FK PACKAGE

(TOP VIEW)

4B 6B

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Summary of content (15 pages)

PAGE 1
SDAS022C − DECEMBER 1982 − REVISED JANUARY 1995 SN54ALS804A, SN54AS804B . . . J PACKAGE SN74ALS804A, SN74AS804B . . . DW OR N PACKAGE (TOP VIEW) High Capacitive-Drive Capability ′ALS804A Has Typical Delay Time of 4 ns (CL = 50 pF) and Typical Power Dissipation of 3.4 mW Per Gate ′AS804B Has Typical Delay Time of 2.
PAGE 2
SDAS022C − DECEMBER 1982 − REVISED JANUARY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SDAS022C − DECEMBER 1982 − REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† TO (OUTPUT) SN54ALS804A tPLH tPHL A or B UNIT SN74ALS804A MIN MAX MIN MAX 2 9 2 7 2 9 2 8 Y ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PAGE 4
SDAS022C − DECEMBER 1982 − REVISED JANUARY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH SN54AS804B TYP† MAX TEST CONDITIONS MIN VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = −18 mA IOH = − 2 mA VCC = 4.5 V IOH = − 3 mA IOH = − 40 mA VOL VCC = 4.5 V II IIH VCC = 5.5 V, VCC = 5.5 V, IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, ICCH ICCL VCC = 5.
PAGE 5
SDAS022C − DECEMBER 1982 − REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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