Datasheet

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FEATURES

DESCRIPTION/ORDERING INFORMATION

DGG OR DGV PACKAGE

(TOP VIEW)

1OE

1Y1

1Y2

GND

1Y3

1Y4

2Y1

2Y2

GND

2Y3

2Y4

3Y1

3Y2

GND

3Y3

3Y4

4Y1

4Y2

GND

4Y3

4Y4

4OE

2OE

1A1

1A2

GND

1A3

1A4

2A1

2A2

GND

2A3

2A4

3A1

3A2

GND

3A3

3A4

4A1

4A2

GND

4A3

4A4

3OE

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and

SN74AUC16244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCES399E – JULY 2002 – REVISED FEBRUARY 2008

www.ti.com

• Member of the Texas Instruments Widebus™

Family

• Optimized for 1.8-V Operation and Is 3.6-V I/O

Tolerant to Support Mixed-Mode Signal

Operation

• I

off

Supports Partial-Power-Down Mode

Operation

• Sub-1-V Operable

• Max t

of 2 ns at 1.8 V

• Low Power Consumption, 20- µ A Max I

• ± 8-mA Output Drive at 1.8 V

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

This 16-bit buffer/driver is operational at 0.8-V to

2.7-V V

, but is designed specifically for 1.65-V to

1.95-V V

operation.

The SN74AUC16244 is designed specifically to

improve the performance and density of 3-state

memory address drivers, clock drivers, and

bus-oriented receivers and transmitters.

symmetrical active-low output-enable ( OE) inputs.

To ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

PACKAGE

(1) (2)

ORDERABLE PART NUMBER TOP-SIDE MARKING

TSSOP – DGG Tape and reel SN74AUC16244DGGR AUC16244

– 40C to 85C TVSOP – DGV Tape and reel SN74AUC16244DGVR MH244

VFBGA – GQL Tape and reel SN74AUC16244GQLR MH244

(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (15 pages)

PAGE 1
SN74AUC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES399E – JULY 2002 – REVISED FEBRUARY 2008 FEATURES 1 DGG OR DGV PACKAGE (TOP VIEW) • Member of the Texas Instruments Widebus™ Family • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation • Ioff Supports Partial-Power-Down Mode Operation • Sub-1-V Operable • Max tpd of 2 ns at 1.8 V • Low Power Consumption, 20-µA Max ICC • ±8-mA Output Drive at 1.
PAGE 2
SN74AUC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.
PAGE 3
SN74AUC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.
PAGE 4
SN74AUC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES399E – JULY 2002 – REVISED FEBRUARY 2008 RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VCC = 0.8 V VIH High-level input voltage MIN MAX 0.8 2.7 UNIT V VCC VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V 0.65 ‫נ‬VCC V 1.7 VCC = 0.8 V 0 0.35 ‫נ‬VCC VIL Low-level input voltage VCC = 1.1 V to 1.95 V VI Input voltage 0 3.6 V VO Output voltage 0 VCC V VCC = 2.3 V to 2.
PAGE 5
SN74AUC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES399E – JULY 2002 – REVISED FEBRUARY 2008 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH VOL VCC TYP (1) MIN MAX IOH = –100 µA 0.8 V to 2.7 V IOH = –0.7 mA 0.8 V IOH = –3 mA 1.1 V 0.8 IOH = –5 mA 1.4 V 1 IOH = –8 mA 1.65 V 1.2 IOH = –9 mA 2.3 V 1.8 IOL = 100 µA 0.8 V to 2.7 V IOL = 0.7 mA 0.8 V IOL = 3 mA 1.1 V 0.
PAGE 6
SN74AUC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES399E – JULY 2002 – REVISED FEBRUARY 2008 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND Open RL LOAD CIRCUIT VCC CL RL V∆ 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 15 pF 15 pF 15 pF 30 pF 30 pF 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω 0.1 V 0.1 V 0.1 V 0.15 V 0.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com (3) 3-Dec-2012 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74AUC16244DGGR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN74AUC16244DGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 SN74AUC16244ZQLR BGA MI CROSTA R JUNI OR ZQL 56 1000 330.0 16.4 4.8 7.3 1.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AUC16244DGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74AUC16244DGVR TVSOP DGV 48 2000 367.0 367.0 38.0 SN74AUC16244ZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 333.2 345.9 28.
PAGE 11
PAGE 12
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 13
PAGE 14
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 15
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.