Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74AUC SM 8

www.ti.com

FEATURES

GND

4 5

GND

Seemechanicaldrawingsfordimensions.

DCTPACKAGE

(TOP VIEW)

DCUPACKAGE

(TOP VIEW)

YEP OR YZP PACKAGE

(BOTTOMVIEW)

DESCRIPTION/ORDERING INFORMATION

SN74AUC2G00

DUAL 2-INPUT POSITIVE-NAND GATE

SCES440C – MAY 2003 – REVISED JANUARY 2007

• Available in the Texas Instruments • Low Power Consumption, 10 µ A at 1.8 V

NanoFree™ Package

• ± 8-mA Output Drive at 1.8 V

• Optimized for 1.8-V Operation and Is 3.6-V I/O

• Latch-Up Performance Exceeds 100 mA Per

Tolerant to Support Mixed-Mode Signal

JESD 78, Class II

Operation

• ESD Protection Exceeds JESD 22

• I

off

Supports Partial-Power-Down Mode

– 2000-V Human-Body Model (A114-A)

Operation

– 200-V Machine Model (A115-A)

• Sub-1-V Operable

– 1000-V Charged-Device Model (C101)

• Max t

of 1.2 ns at 1.8 V

This dual 2-input positive-NAND gate is operational at 0.8-V to 2.7-V V

, but is designed specifically for 1.65-V

to 1.95-V V

operation.

The SN74AUC2G00 performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

(2)

NanoFree™ – WCSP (DSBGA)

Reel of 3000 SN74AUC2G00YZPR _ _ _UA_

0.23-mm Large Bump – YZP (Pb-free)

–40°C to 85°C

SSOP – DCT Reel of 3000 SN74AUC2G00DCTR U00_

VSSOP – DCU Reel of 3000 SN74AUC2G00DCUR U00_

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

DCU: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (15 pages)

PAGE 1
SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C – MAY 2003 – REVISED JANUARY 2007 FEATURES • • • • • • • • Available in the Texas Instruments NanoFree™ Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 1.2 ns at 1.8 V DCT PACKAGE (TOP VIEW) • Low Power Consumption, 10 µA at 1.8 V ±8-mA Output Drive at 1.
PAGE 2
SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C – MAY 2003 – REVISED JANUARY 2007 FUNCTION TABLE (EACH GATE) INPUTS OUTPUT Y A B H H L L X H X L H LOGIC DIAGRAM (POSITIVE LOGIC) 1A 1B 1 7 1Y 2 5 3 2A 2B 2Y 6 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 3.6 V range (2) VI Input voltage –0.5 3.
PAGE 3
SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C – MAY 2003 – REVISED JANUARY 2007 Recommended Operating Conditions VCC (1) Supply voltage VCC = 0.8 V VIH High-level input voltage MIN MAX 0.8 2.7 UNIT V VCC VCC = 1.1 V to 1.95 V 0.65 × VCC VCC = 2.3 V to 2.7 V V 1.7 VCC = 0.8 V 0 VIL Low-level input voltage VCC = 1.1 V to 1.95 V 0.35 × VCC VI Input voltage 0 3.6 V VO Output voltage 0 VCC V VCC = 2.3 V to 2.
PAGE 4
SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C – MAY 2003 – REVISED JANUARY 2007 Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) VCC = 0.8 V A or B Y 8 TYP VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX MIN MAX MIN TYP MAX MIN MAX 1 2.5 0.8 1.6 0.6 0.9 1.2 0.
PAGE 5
SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE www.ti.com SCES440C – MAY 2003 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 2 × VCC S1 RL From Output Under Test Open S1 Open 2 × VCC GND GND CL (see Note A) RL LOAD CIRCUIT VCC CL RL VD 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kW 2 kW 2 kW 2 kW 2 kW 1 kW 500 W 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 15-Dec-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AUC2G00DCUR US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 SN74AUC2G00YZPR DSBGA YZP 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 15-Dec-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AUC2G00DCUR US8 DCU 8 3000 202.0 201.0 28.0 SN74AUC2G00YZPR DSBGA YZP 8 3000 220.0 220.0 35.
PAGE 10
MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0° – 8° 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. B. C. D. 4188781/C 09/02 All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 11
PAGE 12
PAGE 13
PAGE 14
D: Max = 1.918 mm, Min =1.858 mm E: Max = 0.918 mm, Min =0.
PAGE 15
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.