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SN74AUC2G04

DUAL INVERTER GATE

SCES437A – APRIL 2003 – REVISED JUNE 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Available in the Texas Instruments

NanoStar and NanoFree Packages

Optimized for 1.8-V Operation and Is 3.6-V

I/O Tolerant to Support Mixed-Mode Signal

Operation

off

Supports Partial-Power-Down Mode

Operation

Sub 1-V Operable

Max t

of 1.7 ns at 1.8 V

Low Power Consumption, 10 µA at 1.8 V

±8-mA Output Drive at 1.8 V

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

description/ordering information

This dual inverter is operational at 0.8-V to 2.7-V V

, but is designed specifically for 1.65-V to 1.95-V V

operation.

The SN74AUC2G04 performs the Boolean function Y = A

NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the

die as the package.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

‡

–40 C to 85 C

NanoStar – WCSP (DSBGA)

0.23-mm Large Bump – YEP

Tape and reel SN74AUC2G04YEPR

_ _ _UC_

–40

C to 85

NanoFree – WCSP (DSBGA)

0.23-mm Large Bump – YZP (Pb-free)

Tape and reel SN74AUC2G04YZPR

_ _ _UC_

SOT (SOT-23) – DBV Tape and reel SN74AUC2G04DBVR U04_

SOT (SC-70) – DCK Tape and reel SN74AUC2G04DCKR UC_

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

‡

DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one

following character to designate the assembly/test site.

DBV OR DCK PACKAGE

(TOP VIEW)

GND

YEP OR YZP PACKAGE

(BOTTOM VIEW)

NanoStar and NanoFree are trademarks of Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (15 pages)

PAGE 1
SN74AUC2G04 DUAL INVERTER GATE SCES437A – APRIL 2003 – REVISED JUNE 2003 D D D D D D D D D DBV OR DCK PACKAGE (TOP VIEW) Available in the Texas Instruments NanoStar and NanoFree Packages Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub 1-V Operable Max tpd of 1.7 ns at 1.8 V Low Power Consumption, 10 µA at 1.8 V ±8-mA Output Drive at 1.
PAGE 2
SN74AUC2G04 DUAL INVERTER GATE SCES437A – APRIL 2003 – REVISED JUNE 2003 FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H L L H logic diagram (positive logic) 1A 2A 1 6 3 4 1Y 2Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . .
PAGE 3
SN74AUC2G04 DUAL INVERTER GATE SCES437A – APRIL 2003 – REVISED JUNE 2003 recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level input voltage VCC = 0.8 V VCC = 1.1 V to 1.95 V MIN MAX 0.8 2.7 UNIT V VCC 0.65 × VCC VCC = 2.3 V to 2.7 V VCC = 0.8 V V 1.7 0 0.35 × VCC VIL Low-level input voltage VI VO Input voltage 0 3.6 V Output voltage 0 VCC –0.7 V VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V 0.7 VCC = 0.8 V VCC = 1.
PAGE 4
SN74AUC2G04 DUAL INVERTER GATE SCES437A – APRIL 2003 – REVISED JUNE 2003 switching characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V FROM (INPUT) TO (OUTPUT) VCC = 0.8 V TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX A Y 5.4 0.9 3.1 0.7 2 0.6 1 1.7 0.5 1.
PAGE 5
SN74AUC2G04 DUAL INVERTER GATE SCES437A – APRIL 2003 – REVISED JUNE 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) RL VCC 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V LOAD CIRCUIT TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND CL RL 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω V∆ 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 28-Sep-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) SN74AUC2G04DBVR SOT-23 DBV 6 3000 180.0 8.4 SN74AUC2G04YZPR DSBGA YZP 6 3000 178.0 9.2 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 1.02 1.52 0.63 4.0 8.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 28-Sep-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AUC2G04DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0 SN74AUC2G04YZPR DSBGA YZP 6 3000 220.0 220.0 35.
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D: Max = 1.418 mm, Min =1.358 mm E: Max = 0.918 mm, Min =0.
PAGE 15
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.