Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Preset/reset Differential VFQFN 14

www.ti.com

FEATURES

RGY PACKAGE

(TOP VIEW)

1 14

7 8

2CLR

2CLK

2PRE

1CLK

1PRE

1CLR

GND

DESCRIPTION/ORDERING INFORMATION

SN74AUC74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

SCES483A – AUGUST 2003 – REVISED MARCH 2005

• Optimized for 1.8-V Operation and Is 3.6-V I/O

Tolerant to Support Mixed-Mode Signal

Operation

• I

off

Supports Partial-Power-Down Mode

Operation

• Sub-1-V Operable

• Max t

of 1.8 ns at 1.8 V

• Low Power Consumption, 10- µ A Max I

• ± 8-mA Output Drive at 1.8 V

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V V

, but is designed specifically

for 1.65-V to 1.95-V V

operation.

A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for

higher frequencies, the CLR input overrides the PRE input when they are both low.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

–40 ° C to 85 ° C QFN – RGY Tape and reel SN74AUC74RGYR MS74

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

FUNCTION TABLE

INPUTS OUTPUTS

PRE CLR CLK D Q Q

L H X X H L

X L X X L H

H H ↑ H H L

H H ↑ L L H

H H L X Q

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (12 pages)

PAGE 1
SN74AUC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES483A – AUGUST 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 2CLR 3 4 12 2D 5 10 2PRE 9 2Q 11 2CLK 6 7 8 2Q • • • • • 1D 1CLK 1PRE 1Q 1Q 1CLR • RGY PACKAGE (TOP VIEW) Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 1.8 ns at 1.
PAGE 2
SN74AUC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES483A – AUGUST 2003 – REVISED MARCH 2005 LOGIC DIAGRAM, EACH FLIP-FLOP (POSITIVE LOGIC) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 3.6 V VI Input voltage range (2) –0.5 3.
PAGE 3
SN74AUC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES483A – AUGUST 2003 – REVISED MARCH 2005 Recommended Operating Conditions VCC (1) MIN MAX 0.8 2.7 Supply voltage VCC = 0.8 V VIH High-level input voltage UNIT V VCC VCC = 1.1 V to 1.95 V 0.65 × VCC VCC = 2.3 V to 2.7 V V 1.7 VCC = 0.8 V 0 0.35 × VCC VIL Low-level input voltage VCC = 1.1 V to 1.95 V VI Input voltage 0 3.6 V VO Output voltage 0 VCC V VCC = 2.3 V to 2.
PAGE 4
SN74AUC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES483A – AUGUST 2003 – REVISED MARCH 2005 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 0.8 V VCC = 1.2 V ± 0.1 V TYP fclock tw tsu th Clock frequency Pulse duration VCC = 1.5 V ± 0.1 V MIN MAX 100 VCC = 1.8 V ± 0.15 V MIN MAX 225 MIN VCC = 2.5 V ± 0.2 V MAX 250 300 350 CLK high or low 4.6 1.3 0.6 0.5 0.5 CLR low 6.
PAGE 5
SN74AUC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCES483A – AUGUST 2003 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL LOAD CIRCUIT VCC CL RL V∆ 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω 0.1 V 0.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74AUC74RGYR Package Package Pins Type Drawing VQFN RGY 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 3.75 B0 (mm) K0 (mm) P1 (mm) 3.75 1.15 8.0 W Pin1 (mm) Quadrant 12.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AUC74RGYR VQFN RGY 14 3000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.