Datasheet

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SN74AUCH16244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCES391E – MARCH 2002 – REVISED DECEMBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Member of the Texas Instruments

Widebus Family

Optimized for 1.8-V Operation and is 3.6-V

I/O Tolerant to Support Mixed-Mode Signal

Operation

off

Supports Partial-Power-Down Mode

Operation

Sub 1-V Operable

Max t

of 1.8 ns at 1.8 V

Low Power Consumption, 20-µA Max I

±8-mA Output Drive at 1.8 V

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

description/ordering information

This 16-bit buffer/driver is operational at 0.8-V to

2.7-V V

, but is designed specifically for 1.65-V

to 1.95-V V

operation.

The SN74AUCH16244 is designed specifically to

improve the performance and density of 3-state

memory address drivers, clock drivers, and

bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and

symmetrical active-low output-enable (OE

) inputs.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

TSSOP – DGG Tape and reel SN74AUCH16244DGGR AUCH16244

–40°C to 85°C

TVSOP – DGV Tape and reel SN74AUCH16244DGVR MJ244

VFBGA – GQL Tape and reel SN74AUCH16244GQLR MJ244

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Widebus is a trademark of Texas Instruments.

DGG OR DGV PACKAGE

(TOP VIEW)

1OE

1Y1

1Y2

GND

1Y3

1Y4

2Y1

2Y2

GND

2Y3

2Y4

3Y1

3Y2

GND

3Y3

3Y4

4Y1

4Y2

GND

4Y3

4Y4

4OE

2OE

1A1

1A2

GND

1A3

1A4

2A1

2A2

GND

2A3

2A4

3A1

3A2

GND

3A3

3A4

4A1

4A2

GND

4A3

4A4

3OE

Summary of content (16 pages)

PAGE 1
SN74AUCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES391E – MARCH 2002 – REVISED DECEMBER 2002 D D D D D D D D D D DGG OR DGV PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus Family Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub 1-V Operable Max tpd of 1.8 ns at 1.8 V Low Power Consumption, 20-µA Max ICC ±8-mA Output Drive at 1.
PAGE 2
SN74AUCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES391E – MARCH 2002 – REVISED DECEMBER 2002 description/ordering information (continued) Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff.
PAGE 3
SN74AUCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES391E – MARCH 2002 – REVISED DECEMBER 2002 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 3OE 47 2 46 3 44 5 43 6 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 48 4OE 41 8 40 9 38 11 37 12 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 25 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 Pin numbers shown are for the DGG and DGV packages.
PAGE 4
SN74AUCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES391E – MARCH 2002 – REVISED DECEMBER 2002 recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level input voltage VCC = 0.8 V VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V MIN MAX 0.8 2.7 VCC 0.65 × VCC UNIT V V 1.7 VCC = 0.8 V VCC = 1.1 V to 1.95 V 0 0.35 × VCC VIL Low-level input voltage VI VO Input voltage 0 3.6 V Output voltage 0 VCC –0.7 V VCC = 2.3 V to 2.7 V VCC = 0.8 V VCC = 1.
PAGE 5
SN74AUCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES391E – MARCH 2002 – REVISED DECEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 0.8 V to 2.7 V IOH = –100 µA IOH = –0.7 mA VOH VOL II IBHL‡ IBHH§ IBHLO¶ A or OE inputs MIN TYP† MAX 0.8 V 0.55 IOH = –3 mA IOH = –5 mA 1.1 V 0.8 1.4 V 1 IOH = –8 mA IOH = –9 mA 1.65 V 1.2 2.3 V 1.8 IOL = 100 µA IOL = 0.7 mA 0.8 V to 2.7 V V 0.
PAGE 6
SN74AUCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES391E – MARCH 2002 – REVISED DECEMBER 2002 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V FROM (INPUT) TO (OUTPUT) VCC = 0.8 V TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX tpd A Y 5.4 0.8 2.8 0.6 1.9 0.7 1.3 1.8 0.5 1.8 ns ten OE Y 8 1 4.4 0.7 2.6 0.8 1.4 2.5 0.
PAGE 7
SN74AUCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES391E – MARCH 2002 – REVISED DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND Open RL VCC 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V LOAD CIRCUIT CL RL 15 pF 15 pF 15 pF 30 pF 30 pF 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω V∆ 0.1 V 0.1 V 0.1 V 0.15 V 0.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com (3) 3-Dec-2012 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 13-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74AUCH16244DGGR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN74AUCH16244DGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 SN74AUCH16244ZQLR BGA MI CROSTA R JUNI OR ZQL 56 1000 330.0 16.4 4.8 7.3 1.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 13-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AUCH16244DGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74AUCH16244DGVR TVSOP DGV 48 2000 367.0 367.0 38.0 SN74AUCH16244ZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 333.2 345.9 28.
PAGE 12
PAGE 13
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 14
PAGE 15
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 16
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.