Datasheet

1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CCA
1DIR
2DIR
1A1
1A2
2A1
2A2
GND
V
CCB
1OE
2OE
1B1
1B2
2B1
2B2
GND
1 16
8 9
2
3
4
5
6
7
15
14
13
12
11
10
1OE
2OE
1B1
1B2
2B1
2B2
1DIR
2DIR
1A1
1A2
2A1
2A2
GND
V
CCB
GND
V
CCA
RSV PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
D, DGV, OR PW PACKAGE
(TOP VIEW)
1OE
2OE
1B1
1B2
2B1
2DIR
1A1
1A2
2A1
V
CCB
1DIR
V
CCA
4
5
16
6
15
7
14
8
13
3
2
1
2B2
2A2
GND
GND
11
10
9
12
GND
or
FLOAT
SN74AVC4T245
www.ti.com
SCES576E JUNE 2004 REVISED DECEMBER 2011
4-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
1
FEATURES
Control Inputs V
IH
/V
IL
Levels Are Referenced to Latch-Up Performance Exceeds 100 mA Per
V
CCA
Voltage JESD 78, Class II
Fully Configurable Dual-Rail Design Allows ESD Protection Exceeds JESD 22
Each Port to Operate Over the Full 1.2-V to
8000-V Human-Body Model (A114-A)
3.6-V Power-Supply Range
150-V Machine Model (A115-A)
I/Os Are 4.6-V Tolerant
1000-V Charged-Device Model (C101)
I
off
Supports Partial Power-Down-Mode
Operation
Maximim Data Rates
380 Mbps (1.8-V to 3.3-V Translation)
200 Mbps (<1.8-V to 3.3-V Translation)
200 Mbps (Translate to 2.5 V or 1.8 V)
150 Mbps (Translate to 1.5 V)
100 Mbps (Translate to 1.2 V)
DESCRIPTION/ORDERING INFORMATION
This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed
to track V
CCA
. V
CCA
accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V
CCB
. V
CCB
accepts any supply voltage from 1.2 V to 3.6 V. The SN74AVC4T245 is optimized to operate with V
CCA
/V
CCB
set
at 1.4 V to 3.6 V. It is operational with V
CCA
/V
CCB
as low as 1.2 V. This allows for universal low-voltage
bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVC4T245 is designed for asynchronous communication between two data buses. The logic levels of
the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port
outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to
the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level
applied to prevent excess I
CC
and I
CCZ
.
The SN74AVC4T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by V
CCA
.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 20042011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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