Datasheet

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   
      
SCES587B − AUGUST 2004 − REVISED APRIL 2005
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Control Inputs V
IH
/V
IL
Levels Are
Referenced to V
CCA
Voltage
D V
CC
Isolation Feature − If Either V
CC
Input
Is at GND, Both Ports Are in the
High-Impedance State
D Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
D Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
D I
off
Supports Partial-Power-Down Mode
Operation
D I/Os Are 4.6-V Tolerant
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 8000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This 16-bit noninverting bus transceiver uses two
separate configurable power-supply rails. The
SN74AVCH16T245 is optimized to operate with
V
CCA
/V
CCB
set at 1.4 V to 3.6 V. It is operational with V
CCA
/V
CCB
as low as 1.2 V. The A port is designed to track
V
CCA
. V
CCA
accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V
CCB
. V
CCB
accepts
any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between
any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCH16T245 is designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE
) input can be used to disable the outputs so the buses are
effectively isolated.
The SN74AVCH16T245 is designed so that the control pins (1DIR, 2DIR, 1OE
, and 2OE) are supplied by V
CCA
.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP − DGG Tape and reel SN74AVCH16T245GR AVCH16T245
−40
°
C to 85
°
C
TVSOP − DGV Tape and reel SN74AVCH16T245VR WJ245
−40
°
C to 85
°
C
VFBGA − GQL
Tape and reel
SN74AVCH16T245KR
WJ245
VFBGA − ZQL (Pb-free)
Tape and reel
74AVCH16T245ZQLR
WJ245
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
DGG OR DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
V
CCB
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CCB
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
V
CCA
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CCA
2A5
2A6
GND
2A7
2A8
2OE
Copyright 2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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