Datasheet

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SN54BCT8240A, SN74BCT8240A

SCAN TEST DEVICES

WITH OCTAL INVERTING BUFFERS

SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Members of the Texas Instruments

SCOPE

 Family of Testability Products

Octal Test-Integrated Circuits

Functionally Equivalent to ’F240 and

’BCT240 in the Normal-Function Mode

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and

Boundary-Scan Architecture

Test Operation Synchronous to Test

Access Port (TAP)

Implement Optional Test Reset Signal by

Recognizing a Double-High-Level Voltage

(10 V) on TMS Pin

SCOPE

 Instruction Set

– IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, CLAMP,

and HIGHZ

– Parallel-Signature Analysis at Inputs

– Pseudo-Random Pattern Generation

From Outputs

– Sample Inputs/Toggle Outputs

Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Plastic

and Ceramic 300-mil DIPs (JT, NT)

description

The ’BCT8240A scan test devices with octal

buffers are members of the Texas Instruments

SCOPE testability integrated-circuit family. This

family of devices supports IEEE Standard

1149.1-1990 boundary scan to facilitate testing of

complex circuit-board assemblies. Scan access

to the test circuitry is accomplished via the 4-wire

test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the ’F240 and ’BCT240 octal buffers. The test

circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals

or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the

functional operation of the SCOPE octal buffers.

In the test mode, the normal operation of the SCOPE octal buffers is inhibited and the test circuitry is enabled

to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform

boundary-scan test operations, as described in IEEE Standard 1149.1-1990.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

SCOPE is a trademark of Texas Instruments Incorporated.

1OE

1Y1

1Y2

1Y3

1Y4

GND

2Y1

2Y2

2Y3

2Y4

TDO

TMS

2OE

1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

TDI

TCK

SN54BCT8240A . . . JT PACKAGE

SN74BCT8240A ... DW OR NT PACKAGE

(TOP VIEW)

3212827

12 13

2A4

TDI

TCK

TMS

TDO

2Y4

1A2

1A1

2OE

1OE

1Y1

1Y2

426

14 15 16 17

1Y3

1Y4

GND

2Y1

2Y2

2Y3

1A3

1A4

2A1

2A2

2A3

SN54BCT8240A . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 D D D D D description The ’BCT8240A scan test devices with octal buffers are members of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
PAGE 2
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 description (continued) Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs.
PAGE 3
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 functional block diagram Boundary-Scan Register VCC 1OE 1 VCC 1A1 2 23 1Y1 One of Four Channels VCC 2OE 24 VCC 2A1 7 19 2Y1 One of Four Channels Bypass Register Boundary- Control Register VCC TDI 14 VCC 11 TDO Instruction Register VCC TMS 12 VCC TCK TAP Controller 13 Pin numbers shown are for the DW, JT, and NT packages.
PAGE 4
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 Terminal Functions TERMINAL NAME DESCRIPTION 1A1–1A4, 2A1–2A4 Normal-function data inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high level if left unconnected. GND 1OE, 2OE Normal-function output-enable inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high level if left unconnected.
PAGE 5
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 test architecture Serial-test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Standard 1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, TCK and TMS.
PAGE 6
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 state diagram description The TAP controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK. As illustrated, the TAP controller consists of 16 states.
PAGE 7
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 Exit1-DR, Exit2-DR The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.
PAGE 8
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 register overview With the exception of the bypass register, any test register may be thought of as a serial-shift register with a shadow latch on each bit. The bypass register differs in that it contains only a shift register.
PAGE 9
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 Table 1.
PAGE 10
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 Table 2.
PAGE 11
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 control boundary to high impedance This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR.
PAGE 12
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 boundary-control-register opcode description The BCR opcodes are decoded from BCR bits 1–0, as shown in Table 3. The selected test operation is performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms. Table 3.
PAGE 13
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 parallel-signature analysis (PSA) Data appearing at the device input terminals is compressed into a 16-bit parallel signature in the shift-register elements of the BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip logic.
PAGE 14
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 timing description All test operations of the ’BCT8240A are synchronous to TCK. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output terminals on the falling edge of TCK.
PAGE 15
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Test-Logic-Reset Select-IR-Scan Select-DR-Scan Update-DR ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Exit1-DR Capture-DR Update-IR Select-DR-Scan ÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Exit1-IR Shift-IR Capture-IR Select-IR-Scan TAP Controller State Select-DR-Scan TDO ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
PAGE 16
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 recommended operating conditions SN54BCT8240A SN74BCT8240A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIHH VIL Double-high-level input voltage Low-level input voltage 0.8 0.
PAGE 17
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK Any Y VCC = 4.5 V, VCC = 4.75 V, II = –18 mA IOH = –3 mA VCC = 4.5 V IOH = –3 mA IOH = –12 mA VCC = 4.75 V, IOH = –15 mA IOH = –1 mA VOH TDO Any Y II IIH IIHH IIL IOZH TMS Any Y MIN –1.2 2.4 3.4 2.4 3.4 2 3.2 2 3.1 2.7 3.4 2.7 3.4 2.5 3.4 2.
PAGE 18
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 9) VCC = 5 V, TA = 25°C fclock Clock frequency tw Pulse duration tsu th Setup time Hold time TCK SN54BCT8240A SN74BCT8240A MIN MAX MIN MAX MIN MAX 0 20 0 20 0 20 TCK high or low 25 25 25 TMS double high 50* 50* 5
PAGE 19
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 9) FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y PARAMETER VCC = 5 V, TA = 25°C MIN TYP MAX SN54BCT8240A SN74BCT8240A MIN MAX MIN MAX 2.5 5.7 7.5 2.5 10 2.5 9 2.5 5.2 7 2.5 9 2.
PAGE 20
SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996 PARAMETER MEASUREMENT INFORMATION 7 V (tPZL, tPLZ, O.C.) S1 Open (all others) R1 From Output Under Test From Output Under Test Test Point CL (see Note A) Test Point CL (see Note A) R2 R1 RL = R1 = R2 LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR 3-STATE AND OPEN-COLLECTOR OUTPUTS Timing Input 3V High-Level Pulse 3V 1.5 V 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PAGE 23
MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.008 (0,20) 0.
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