Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Switch FET bus switch Single supply TVSOP 48

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FEATURES

1OE

1B1

1B2

GND

1B3

1B4

2B1

2B2

GND

2B3

2B4

3B1

3B2

GND

3B3

3B4

4B1

4B2

GND

4B3

4B4

4OE

2OE

1A1

1A2

GND

1A3

1A4

2A1

2A2

GND

2A3

2A4

3A1

3A2

GND

3A3

3A4

4A1

4A2

GND

4A3

4A4

3OE

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

SN74CB3Q16244

16-BIT FET BUS SWITCH

2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH

SCDS168 – MAY 2004 – REVISED MARCH 2005

• High-Bandwidth Data Path (up to 500 MHz

(1)

)

• 5-V Tolerant I/Os With Device Powered Up or

Powered Down

• Low and Flat ON-State Resistance (r

)

Characteristics Over Operating Range

= 5 Ω Typ)

• Rail-to-Rail Switching on Data I/O Ports

– 0- to 5-V Switching With 3.3-V V

– 0- to 3.3-V Switching With 2.5-V V

• Bidirectional Data Flow With Near-Zero

Propagation Delay

• Low Input/Output Capacitance Minimizes

Loading and Signal Distortion

io(OFF)

= 4 pF Typ)

• Fast Switching Frequency (f

= 20 MHz Max)

• Data and Control Inputs Provide Undershoot

Clamp Diodes

• Low Power Consumption (I

= 1 mA Typ)

• V

Operating Range From 2.3 V to 3.6 V

• Data I/Os Support 0- to 5-V Signaling Levels

(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)

• Control Inputs Can Be Driven by TTL or

5-V/3.3-V CMOS Outputs

• I

off

Supports Partial-Power-Down Mode

Operation

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Performance Tested Per JESD 22

– 2000-V Human-Body Model

(A114-B, Class II)

– 1000-V Charged-Device Model (C101)

• Supports Both Digital and Analog

Applications: PCI Interface, Differential Signal

Interface, Memory Interleaving, Bus Isolation,

Low-Distortion Signal Gating

(1) For additional information regarding the performance charac-

teristics of the CB3Q family, refer to the TI application report,

CBT-C, CB3T, and CB3Q Signal-Switch Families, literature

number SCDA008.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (15 pages)

PAGE 1
www.ti.com SN74CB3Q16244 16-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH FEATURES • • • • • • • • • • • • • • • • (1) High-Bandwidth Data Path (up to 500 MHz (1)) 5-V Tolerant I/Os With Device Powered Up or Powered Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 5 Ω Typ) Rail-to-Rail Switching on Data I/O Ports – 0- to 5-V Switching With 3.3-V VCC – 0- to 3.3-V Switching With 2.
PAGE 2
SN74CB3Q16244 16-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH www.ti.com SCDS168 – MAY 2004 – REVISED MARCH 2005 DESCRIPTION/ORDERING INFORMATION The SN74CB3Q16244 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports.
PAGE 3
SN74CB3Q16244 16-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH www.ti.com SCDS168 – MAY 2004 – REVISED MARCH 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 47 1A1 2 SW 43 1A4 41 1B1 2A1 1B4 2A4 6 SW 37 1 2B1 12 2B4 SW 48 1OE 2OE 36 3A1 13 SW 30 3B1 4A1 3B4 4A4 17 32 3A4 3OE 8 SW SW 19 23 26 25 4OE 4B1 SW SW 4B4 24 SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW) A B VCC Charge Pump EN(1) (1) EN is the internal enable signal applied to the switch.
PAGE 4
SN74CB3Q16244 16-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH www.ti.com SCDS168 – MAY 2004 – REVISED MARCH 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range (2) –0.5 4.6 V VIN Control input voltage range (2) (3) –0.
PAGE 5
SN74CB3Q16244 16-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH www.ti.com SCDS168 – MAY 2004 – REVISED MARCH 2005 Electrical Characteristics (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK MIN TYP (2) TEST CONDITIONS VCC = 3.6 V, II = –18 mA VCC = 3.6 V, VIN = 0 to 5.5 V IOZ (3) VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0 ICC VCC = 3.
PAGE 6
SN74CB3Q16244 16-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH www.ti.com SCDS168 – MAY 2004 – REVISED MARCH 2005 ron – ON-State Resistance – 16 VCC = 3.3 V TA = 25°C IO = −15 mA 14 12 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VI − V Figure 1. Typical ron vs VI 12 VCC = 3.3 V TA = 25°C A and B Ports Open 10 ICC − mA 8 6 4 One OE Switching 2 0 0 2 4 6 8 10 12 14 OE Switching Frequency − MHz Figure 2.
PAGE 7
SN74CB3Q16244 16-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH www.ti.com SCDS168 – MAY 2004 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 2 × VCC Input Generator S1 RL VO VI 50 Ω 50 Ω VG2 CL (see Note A) RL TEST VCC S1 RL VI CL tpd(s) 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω VCC or GND VCC or GND 30 pF 50 pF tPLZ/tPZL 2.5 V ± 0.2 V 3.3 V ± 0.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.6 15.8 1.8 12.0 24.0 Q1 SN74CB3Q16244DGGR TSSOP DGG 48 2000 330.0 24.4 SN74CB3Q16244DGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 SN74CB3Q16244DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CB3Q16244DGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74CB3Q16244DGVR TVSOP DGV 48 2000 367.0 367.0 38.0 SN74CB3Q16244DLR SSOP DL 48 1000 367.0 367.0 55.
PAGE 12
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 13
PAGE 14
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 15
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.