Datasheet


   
      
SCDS122A − JULY 2003 − REVISED OCTOBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Undershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
D Bidirectional Data Flow, With Near-Zero
Propagation Delay
D Low ON-State Resistance (r
on
)
Characteristics (r
on
= 3 Ω Typical)
D Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(C
io(OFF)
= 5 pF Typical)
D Data and Control Inputs Provide
Undershoot Clamp Diodes
D Low Power Consumption
(I
CC
= 3 µA Max)
D V
CC
Operating Range From 4 V to 5.5 V
D Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
D Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
D I
off
Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
D Supports Both Digital and Analog
Applications: USB Interface, Bus Isolation,
Low-Distortion Signal Gating
D, DB, DGV, OR PW PACKAGE
(TOP VIEW)
NC − No internal connection
DBQ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
1OE
1A
1B
2OE
2A
2B
GND
V
CC
4OE
4A
4B
3OE
3A
3B
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1B
2OE
2A
2B
GND
V
CC
4OE
4A
4B
3OE
3A
3B
RGY PACKAGE
(TOP VIEW)
114
78
2
3
4
5
6
13
12
11
10
9
4OE
4A
4B
3OE
3A
1A
1B
2OE
2A
2B
1OE
3B
V
G
ND
CC
description/ordering information
The SN74CBT3125C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r
on
),
allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the
SN74CBT3125C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring
that the switch remains in the proper OFF state.
The SN74CBT3125C is organized as four 1-bit bus switches with separate output-enable (1OE
, 2OE, 3OE,
4OE
) inputs. It can be used as four 1-bit bus switches or as one 4-bit bus switch. When OE is low, the associated
1-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports.
When OE
is high, the associated 1-bit bus switch is OFF, and the high-impedance state exists between the A
and B ports.
This device is fully specified for partial-power-down applications using I
off
. The I
off
feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
Copyright  2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
  !"#$ % &'!!($ #%  )'*+&#$ ,#$(-
!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2  #++ )#!#"($(!%-