Datasheet

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SN74CBT3126

QUADRUPLE FET BUS SWITCH

SCDS020K − MAY 1995 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Standard ’126-Type Pinout (D, DB, DGV,

and PW Packages)

D 5-Ω Switch Connection Between Two Ports

D TTL-Compatible Input Levels

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

1OE

2OE

GND

4OE

3OE

D, DB, DGV, OR PW PACKAGE

(TOP VIEW)

1OE

2OE

GND

4OE

3OE

DBQ PACKAGE

(TOP VIEW)

NC − No internal connection

RGY PACKAGE

(TOP VIEW)

114

4OE

3OE

2OE

1OE

GND

description/ordering information

The SN74CBT3126 quadruple FET bus switch features independent line switches. Each switch is disabled

when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a

pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the

driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Tape and reel SN74CBT3126RGYR CU126

SOIC D

Tube SN74CBT3126D

CBT3126

SOIC − D

Tape and reel SN74CBT3126DR

CBT3126

40°Cto85°C

SSOP − DB Tape and reel SN74CBT3126DBR CU126

−40°C to 85°C

SSOP (QSOP) − DBQ Tape and reel SN74CBT3126DBQR CU126

TSSOP PW

Tube SN74CBT3126PW

CU126

TSSOP − PW

Tape and reel SN74CBT3126PWR

CU126

TVSOP − DGV Tape and reel SN74CBT3126DGVR CU126

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

FUNCTION TABLE

(each bus switch)

INPUT

FUNCTION

L Disconnect

H A = B

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (19 pages)

PAGE 1
SN74CBT3126 QUADRUPLE FET BUS SWITCH SCDS020K − MAY 1995 − REVISED OCTOBER 2003 D Standard ’126-Type Pinout (D, DB, DGV, D, DB, DGV, OR PW PACKAGE (TOP VIEW) 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4B 3OE 3A 3B VCC 14 2 1 1A 1B 2OE 2A 2B NC 1OE 1A 1B 2OE 2A 2B GND 14 2 13 4OE 3 12 4A 4 11 4B 5 10 3OE 9 3A 6 7 8 3B 1 DBQ PACKAGE (TOP VIEW) RGY PACKAGE (TOP VIEW) 1OE 1OE 1A 1B 2OE 2A 2B GND JESD 17 GND D D TTL-Compatible Input Levels D Latch-Up Performance Exceeds 250 mA
PAGE 2
SN74CBT3126 QUADRUPLE FET BUS SWITCH SCDS020K − MAY 1995 − REVISED OCTOBER 2003 logic diagram (positive logic) 2 3 1B 1A 1 1OE 2A 2OE 5 6 4 9 8 3B 3A 3OE 10 12 11 4A 4OE 2B 4B 13 Pin numbers shown are for the D, DB, DGV, PW, and RGY packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 3
SN74CBT3126 QUADRUPLE FET BUS SWITCH SCDS020K − MAY 1995 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VIK VCC = 4.5 V, II = −18 mA II VCC = 5.5 V, VI = 5.5 V or GND ICC VCC = 5.5 V, IO = 0, VI = VCC or GND One input at 3.4 V, Other inputs at VCC or GND ΔICC‡ Control inputs VCC = 5.
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SN74CBT3126 QUADRUPLE FET BUS SWITCH SCDS020K − MAY 1995 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 7V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V Output Control LOAD CIRCUIT 1.5 V 1.5 V 0V tPZL 3V Input 1.5 V 1.5 V 0V tPLH 1.5 V 3.5 V 1.5 V 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74CBT3126DBR Package Package Pins Type Drawing SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74CBT3126DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74CBT3126PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CBT3126DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74CBT3126DR SOIC D 14 2500 367.0 367.0 38.0 SN74CBT3126PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74CBT3126RGYR VQFN RGY 14 3000 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 19
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.