Datasheet


   
      
SCDS132A − SEPTEMBER 2003 − REVISED OCTOBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Undershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
D Bidirectional Data Flow, With Near-Zero
Propagation Delay
D Low ON-State Resistance (r
on
)
Characteristics (r
on
= 3 Ω Typical)
D Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(C
io(OFF)
= 5 pF Typical)
D Data and Control Inputs Provide
Undershoot Clamp Diodes
D Low Power Consumption
(I
CC
= 3 µA Max)
D V
CC
Operating Range From 4 V to 5.5 V
D Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
D Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
D I
off
Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
D Supports Both Digital and Analog
Applications: PCI Interface, Memory
Interleaving, Bus Isolation, Low-Distortion
Signal Gating
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
1OE
1B1
1A1
1A2
1B2
1B3
1A3
1A4
1B4
1B5
1A5
GND
V
CC
2B5
2A5
2A4
2B4
2B3
2A3
2A2
2B2
2B1
2A1
2OE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
description/ordering information
The SN74CBT3384C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r
on
),
allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the
SN74CBT3384C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring
that the switch remains in the proper OFF state.
The SN74CBT3384C is organized as two 5-bit bus switches with separate output-enable (1OE
, 2OE) inputs.
It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE
is low, the associated 5-bit bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE
is high, the associated 5-bit bus switch is OFF, and the high-impedance state exists between the A and B
ports.
Copyright  2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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