Datasheet

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SCDS128A − SEPTEMBER 2003 − REVISED OCTOBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Undershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
D Integrated Diode to V
CC
Provides 5-V Input
Down To 3.3-V Output Level Shift
D Bidirectional Data Flow, With Near-Zero
Propagation Delay
D Low ON-State Resistance (r
on
)
Characteristics (r
on
= 3 Ω Typical)
D Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(C
io(OFF)
= 5 pF Typical)
D Data and Control Inputs Provide
Undershoot Clamp Diodes
D V
CC
Operating Range From 4.5 V to 5.5 V
D Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
D Control Inputs Can be Driven by TTL or
5-V/3.3-V CMOS Outputs
D I
off
Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
D Supports Both Digital and Analog
Applications: USB Interface, Memory
Interleaving, Bus Isolation, Low-Distortion
Signal Gating
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OE
1A
1B
GND
V
CC
2OE
2B
2A
description/ordering information
The SN74CBTD3306C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r
on
),
allowing for minimal propagation delay. This device features an integrated diode in series with V
CC
to provide
level shifting for 5-V input down to 3.3-V output levels. Active Undershoot-Protection Circuitry on the A and B
ports of the SN74CBTD3306C provides protection for undershoot up to −2 V by sensing an undershoot event
and ensuring that the switch remains in the proper OFF state.
The SN74CBTD3306C is organized as two 1-bit bus switches with separate output-enable (1OE
, 2OE) inputs.
It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE
is low, the associated 1-bit bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE
is high, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − D
Tube SN74CBTD3306CD
CC306C
−40°C to 85°C
SOIC − D
Tape and reel SN74CBTD3306CDR
CC306C
−40°C to 85°C
TSSOP − PW
Tube SN74CBTD3306CPW
CC306C
TSSOP − PW
Tape and reel SN74CBTD3306CPWR
CC306C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
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Copyright  2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.