Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Switch FET bus switch Single supply TSSOP 14



    

SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

D Standard ’125-Type Pinout

D 5-Ω Switch Connection Between Two Ports

D Rail-to-Rail Switching on Data I/O Ports

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D, DGV, NS, OR PW PACKAGE

(TOP VIEW)

NC − No internal connection

DBQ PACKAGE

(TOP VIEW)

1OE

2OE

GND

4OE

3OE

1OE

2OE

GND

4OE

3OE

RGY PACKAGE

(TOP VIEW)

114

4OE

3OE

2OE

1OE

GND

description/ordering information

The SN74CBTLV3125 quadruple FET bus switch features independent line switches. Each switch is disabled

when the associated output-enable (OE

) input is high.

This device is fully specified for partial-power-down applications using I

off

. The I

off

feature ensures that

damaging current will not backflow through the device when it is powered down. The device has isolation during

power off.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Tape and reel SN74CBTLV3125RGYR CL125

SOIC − D

Tube SN74CBTLV3125D

CBTLV3125

SOIC − D

Tape and reel SN74CBTLV3125DR

CBTLV3125

−40°C to 85°C

SOP − NS Tape and reel SN74CBTLV3125NSR CBTLV3125

−40 C to 85 C

SSOP (QSOP) − DBQ Tape and reel SN74CBTLV3125DBQR CL125

TSSOP − PW Tape and reel SN74CBTLV3125PWR CL125

TVSOP − DGV Tape and reel SN74CBTLV3125DGVR CL125

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

  !"#$ % &'!!($ #%  )'*+&#$ ,#$(-

!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($%

%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(

$(%$2  #++ )#!#"($(!%-

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (20 pages)

PAGE 1
SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003 D Standard ’125-Type Pinout D 5-Ω Switch Connection Between Two Ports D Rail-to-Rail Switching on Data I/O Ports 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4B 3OE 3A 3B 1 1A 1B 2OE 2A 2B DBQ PACKAGE (TOP VIEW) VCC 14 2 NC 1OE 1A 1B 2OE 2A 2B GND 14 2 13 4OE 3 12 4A 4 11 4B 5 10 3OE 9 3A 6 7 8 3B 1 Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II RGY PACKAGE (TOP VIEW)
PAGE 2
SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003 FUNCTION TABLE (each bus switch) INPUT OE FUNCTION L A port = B port H Disconnect logic diagram (positive logic) 3 2 1A 1OE 1B SW 1 6 5 2A 2B SW 4 2OE 9 8 3A 3B SW 10 3OE 12 11 4A SW 4B 13 4OE Pin numbers shown are for the D, DGV, NS, PW, and RGY packages.
PAGE 3
SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.
PAGE 4
SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VIK II VCC = 3 V, VCC = 3.6 V, II = −18 mA VI = VCC or GND Ioff ICC VCC = 0, VCC = 3.6 V, VI or VO = 0 to 3.6 V IO = 0, VI = VCC or GND One input at 3 V, Other inputs at VCC or GND ∆ICC‡ Control inputs Ci Control inputs Cio(OFF) VCC = 3.
PAGE 5
SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC RL From Output Under Test S1 Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL LOAD CIRCUIT VCC CL RL V∆ 2.5 V ±0.2 V 3.3 V ±0.3 V 30 pF 50 pF 500 Ω 500 Ω 0.15 V 0.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74CBTLV3125DGVR Package Package Pins Type Drawing TVSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74CBTLV3125DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74CBTLV3125PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CBTLV3125DGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74CBTLV3125DR SOIC D 14 2500 367.0 367.0 38.0 SN74CBTLV3125PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74CBTLV3125RGYR VQFN RGY 14 3000 367.0 367.0 35.
PAGE 10
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 11
PAGE 12
PAGE 13
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 19
PAGE 20
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.