Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Switch FET bus switch Single supply SOIC 14



    

SCDS038I − DECEMBER 1997 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Standard ’126-Type Pinout

D 5-Ω Switch Connection Between Two Ports

D Rail-to-Rail Switching on Data I/O Ports

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-up Performance Exceeds 100 mA per

JESD 78, Class II

1OE

2OE

GND

4OE

3OE

D, DGV, OR PW PACKAGE

(TOP VIEW)

1OE

2OE

GND

4OE

3OE

DBQ PACKAGE

(TOP VIEW)

NC − No internal connection

RGY PACKAGE

(TOP VIEW)

114

4OE

3OE

2OE

1OE

GND

description/ordering information

The SN74CBTLV3126 quadruple FET bus switch features independent line switches. Each switch is disabled

when the associated output-enable (OE) input is low.

This device is fully specified for partial-power-down applications using I

off

. The I

off

feature ensures that

damaging current will not backflow through the device when it is powered down. The device has isolation during

power off.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a

pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Tape and reel SN74CBTLV3126RGYR CL126

SOIC − D

Tube SN74CBTLV3126D

CBTLV3126

−40°C to 85°C

SOIC − D

Tape and reel SN74CBTLV3126DR

CBTLV3126

−40

C to 85

SSOP (QSOP) − DBQ Tape and reel SN74CBTLV3126DBQR CL126

TSSOP − PW Tape and reel SN74CBTLV3126PWR CL126

TVSOP − DGV Tape and reel SN74CBTLV3126DGVR CL126

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

(each bus switch)

INPUT

FUNCTION

L Disconnect

H A port = B port

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (20 pages)

PAGE 1
SCDS038I − DECEMBER 1997 − REVISED OCTOBER 2003 D Standard ’126-Type Pinout D 5-Ω Switch Connection Between Two Ports D Rail-to-Rail Switching on Data I/O Ports D, DGV, OR PW PACKAGE (TOP VIEW) 3 12 4 11 5 10 6 9 7 8 DBQ PACKAGE (TOP VIEW) VCC 4OE 4A 4B 3OE 3A 3B VCC 13 1 1A 1B 2OE 2A 2B NC 1OE 1A 1B 2OE 2A 2B GND 14 2 13 4OE 3 12 4A 4 11 4B 5 10 3OE 9 3A 6 7 8 3B 14 2 Operation Latch-up Performance Exceeds 100 mA per JESD 78, Cl
PAGE 2
SCDS038I − DECEMBER 1997 − REVISED OCTOBER 2003 logic diagram (positive logic) 3 2 1A 1B SW 1 1OE 6 5 2A 2B SW 4 2OE 8 9 3A 3OE 3B SW 10 11 12 4A SW 4B 13 4OE Pin numbers shown are for the D, DGV, PW, and RGY packages.
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SCDS038I − DECEMBER 1997 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.
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SCDS038I − DECEMBER 1997 − REVISED OCTOBER 2003 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd† A or B B or A ten OE A or B PARAMETER VCC = 2.5 V ± 0.2 V MIN MAX VCC = 3.3 V ± 0.3 V MIN 0.15 1.6 4.5 1.9 UNIT MAX 0.25 ns 4.2 ns tdis A or B 1.3 4.7 1 4.
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SCDS038I − DECEMBER 1997 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC RL From Output Under Test S1 Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL LOAD CIRCUIT VCC CL RL V∆ 2.5 V ±0.2 V 3.3 V ±0.3 V 30 pF 50 pF 500 Ω 500 Ω 0.15 V 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74CBTLV3126DGVR Package Package Pins Type Drawing TVSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74CBTLV3126DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74CBTLV3126PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CBTLV3126DGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74CBTLV3126DR SOIC D 14 2500 367.0 367.0 38.0 SN74CBTLV3126PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74CBTLV3126RGYR VQFN RGY 14 3000 367.0 367.0 35.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.