Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Multiplexer, demux FET multiplexer/demultiplexer Single supply SOIC 16 N

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SCDS039H − DECEMBER 1997 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Functionally Equivalent to QS3253

D 5-Ω Switch Connection Between Two Ports

D Rail-to-Rail Switching on Data I/O Ports

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

1OE

1B4

1B3

1B2

1B1

GND

2OE

2B4

2B3

2B2

2B1

D, DBQ, DGV, OR PW PACKAGE

(TOP VIEW)

RGY PACKAGE

(TOP VIEW)

116

2OE

2B4

2B3

2B2

2B1

1B4

1B3

1B2

1B1

1OE

GND

description/ordering information

The SN74CBTLV3253 is a dual 1-of-4 high-speed FET multiplexer/demultiplexer. The low on-state resistance

of the switch allows connections to be made with minimal propagation delay.

The select (S0, S1) inputs control the data flow. The FET multiplexers/demultiplexers are disabled when the

associated output-enable (OE

) input is high.

This device is fully specified for partial-power-down applications using I

off

. The I

off

feature ensures that

damaging current will not backflow through the device when it is powered down. The device has isolation during

power off.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Tape and reel SN74CBTLV3253RGYR CL253

SOIC − D

Tube SN74CBTLV3253D

CBTLV3253

−40°C to 85°C

SOIC − D

Tape and reel SN74CBTLV3253DR

CBTLV3253

−40°C to 85°C

SSOP (QSOP) − DBQ Tape and reel SN74CBTLV3253DBQR CL253

TSSOP − PW Tape and reel SN74CBTLV3253PWR CL253

TVSOP − DGV Tape and reel SN74CBTLV3253DGVR CL253

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (19 pages)

PAGE 1
SCDS039H − DECEMBER 1997 − REVISED OCTOBER 2003 D Functionally Equivalent to QS3253 D 5-Ω Switch Connection Between Two Ports D Rail-to-Rail Switching on Data I/O Ports D Ioff Supports Partial-Power-Down Mode D Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 2OE S0 2B4 2B3 2B2 2B1 2A S1 1B4 1B3 1B2 1B1 1A VCC 16 2 1 16 15 2OE 14 S0 2 3 13 2B4 12 2B3 4 5 11 2B2 10
PAGE 2
SCDS039H − DECEMBER 1997 − REVISED OCTOBER 2003 FUNCTION TABLE (each multiplexer/demultiplexer) INPUTS FUNCTION OE S1 S0 L L L A port = B1 port L L H A port = B2 port L H L A port = B3 port L H H A port = B4 port H X X Disconnect logic diagram (positive logic) 7 1A 6 SW 5 SW 1B1 1B2 4 SW 1B3 3 1B4 SW 9 10 2A 2B1 SW 11 SW 2B2 12 2B3 SW 13 SW 14 S0 2 S1 1 1OE 2OE 2 15 POST OFFICE BOX 655303 • DALLAS, TEX
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SCDS039H − DECEMBER 1997 − REVISED OCTOBER 2003 simplified schematic, each FET switch A B (OE) absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
SCDS039H − DECEMBER 1997 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK II VCC = 3 V, VCC = 3.6 V, II = −18 mA VI = VCC or GND Ioff ICC VCC = 0, VCC = 3.6 V, VI or VO = 0 to 3.6 V IO = 0, VI = VCC or GND VCC = 3.6 V, VI = 3 V or 0 One input at 3 V, VO = 3 V or 0, OE = VCC VCC = 2.3 V, TYP at VCC = 2.
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SCDS039H − DECEMBER 1997 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC RL From Output Under Test S1 Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL VCC 2.5 V ±0.2 V 3.3 V ±0.3 V LOAD CIRCUIT CL RL 30 pF 50 pF 500 Ω 500 Ω V∆ 0.15 V 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74CBTLV3253DGVR Package Package Pins Type Drawing TVSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74CBTLV3253DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74CBTLV3253PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CBTLV3253DGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74CBTLV3253DR SOIC D 16 2500 333.2 345.9 28.6 SN74CBTLV3253PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74CBTLV3253RGYR VQFN RGY 16 3000 367.0 367.0 35.
PAGE 10
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.