Datasheet

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

    

SCDS041H − DECEMBER 1997 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 5-Ω Switch Connection Between Two Ports

D Rail-to-Rail Switching on Data I/O Ports

D I

off

Supports Partial-Power-Down Mode

Operation

D Flow-Through Architecture Optimizes PCB

Layout

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

description/ordering information

The SN74CBTLV3861 provides ten bits of

high-speed bus switching. The low on-state

resistance of the switch allows connections to be

made with minimal propagation delay.

The device is organized as one 10-bit bus switch.

When output enable (OE

) is low, the 10-bit bus

switch is on, and port A is connected to port B.

When OE

is high, the switch is open, and the

high-impedance state exists between the two

ports.

This device is fully specified for partial-power-down applications using I

off

. The I

off

feature ensures that

damaging current will not backflow through the device when it is powered down. The device has isolation during

power off.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QSOP − DBQ Tape and reel SN74CBTLV3861DBQR CBTLV3861

SOIC − DW

Tube SN74CBTLV3861DW

CBTLV3861

−40°C to 85°C

SOIC − DW

Tape and reel SN74CBTLV3861DWR

CBTLV3861

−40°C to 85°C

SOP − NS Tape and reel SN74CBTLV3861NSR CBTLV3861

TSSOP − PW Tape and reel SN74CBTLV3861PWR CL861

TVSOP − DGV Tape and reel SN74CBTLV3861DGVR CL861

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

FUNCTION TABLE

INPUT

FUNCTION

L A port = B port

H Disconnect

DBQ, DGV, DW, NS, OR PW PACKAGE

(TOP VIEW)

A10

GND

B10

NC − No internal connection

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (17 pages)

PAGE 1
SCDS041H − DECEMBER 1997 − REVISED OCTOBER 2003 D 5-Ω Switch Connection Between Two Ports D Rail-to-Rail Switching on Data I/O Ports D Ioff Supports Partial-Power-Down Mode D D DBQ, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) NC A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 GND Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 provides ten bits of high-speed bus switc
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SCDS041H − DECEMBER 1997 − REVISED OCTOBER 2003 logic diagram (positive logic) 2 A1 22 B1 SW 11 A10 13 SW B10 23 OE simplified schematic, each FET switch A B (OE) absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . .
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SCDS041H − DECEMBER 1997 − REVISED OCTOBER 2003 recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Low-level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 2.3 3.6 1.7 UNIT V V 2 0.7 0.
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SCDS041H − DECEMBER 1997 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC RL From Output Under Test S1 Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL CL 30 pF 50 pF VCC 2.5 V ±0.2 V 3.3 V ±0.3 V LOAD CIRCUIT V∆ 0.15 V 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.0 2.1 8.0 16.0 Q1 SN74CBTLV3861DBQR SSOP DBQ 24 2500 330.0 16.4 SN74CBTLV3861DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74CBTLV3861DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CBTLV3861DBQR SSOP DBQ 24 2500 367.0 367.0 38.0 SN74CBTLV3861DGVR TVSOP DGV 24 2000 367.0 367.0 35.0 SN74CBTLV3861DWR SOIC DW 24 2000 367.0 367.0 45.0 SN74CBTLV3861NSR SO NS 24 2000 367.0 367.0 45.0 SN74CBTLV3861PWR TSSOP PW 24 2000 367.0 367.0 38.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.