Datasheet

SN74F126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SDFS017B – JANUARY 1989 – REVISED NOVEMBER 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4.5-V to 5.5-V V
CC
Operation
Max t
pd
of 6.5 ns at 5 V
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
description/ordering information
The SN74F126 bus buffer features independent
line drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE)
input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N Tube SN74F126N SN74F126N
0°Cto70°C
SOIC D
Tube SN74F126D
F126
0°C
to
70°C
SOIC
–
D
Tape and reel SN74F126DR
F126
SOP – NS Tape and reel SN74F126NSR 74F126
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE A
Y
H H H
H LL
L X Z
Copyright  2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.