Datasheet

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SN74F161A

SYNCHRONOUS 4-BIT BINARY COUNTER

SDFS056B – MARCH 1987 – REVISED AUGUST 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Internal Look-Ahead Circuitry for Fast

Counting

Carry Output for N-Bit Cascading

Fully Synchronous Operation for Counting

description

This synchronous, presettable, 4-bit binary

counter has internal carry look-ahead circuitry

for use in high-speed counting designs.

Synchronous operation is provided by having all

flip-flops clocked simultaneously so that the

outputs change coincident with each other when

so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the

output counting spikes that are normally associated with asynchronous (ripple-clock) counters. However,

counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four

flip-flops on the rising (positive-going) edge of CLK.

This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because

presetting is synchronous, a low logic level at the load (LOAD

) input disables the counter and causes the outputs

to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.

The clear function is asynchronous, and a low logic level at the clear (CLR

) input sets all four of the flip-flop

outputs to low, regardless of the levels of CLK, LOAD

, ENP, and ENT.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without

additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and

ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a

high-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used

to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.

The SN74F161A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD

that modify the

operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter

(whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold

times.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – N Tube SN74F161AN SN74F161AN

0°Cto70°C

SOIC D

Tube SN74F161AD

F161A

0°C

70°C

SOIC

–

Tape and reel SN74F161ADR

F161A

SSOP – DB Tape and reel SN74F161ADBR F161A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CLR

CLK

ENP

GND

RCO

ENT

LOAD

D, DB, OR N PACKAGE

(TOP VIEW)

Summary of content (17 pages)

PAGE 1
SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056B – MARCH 1987 – REVISED AUGUST 2001 D D D D, DB, OR N PACKAGE (TOP VIEW) Internal Look-Ahead Circuitry for Fast Counting Carry Output for N-Bit Cascading Fully Synchronous Operation for Counting CLR CLK A B C D ENP GND description 1 16 2 15 3 14 4 13 5 VCC RCO QA QB QC QD ENT LOAD 12 This synchronous, presettable, 4-bit binary 6 11 counter has internal carry look-ahead circuitry 7 10 for use in high-speed counting designs.
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SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056B – MARCH 1987 – REVISED AUGUST 2001 state diagram 0 2 3 4 15 5 14 6 13 7 12 2 1 11 POST OFFICE BOX 655303 10 9 • DALLAS, TEXAS 75265 8
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SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056B – MARCH 1987 – REVISED AUGUST 2001 logic diagram (positive logic) CLR LOAD ENT ENP 1 9 10 15 7 RCO R 14 CLK A 2 3 G2 QA 1, 2T/C3 1, 3D M1 R 13 G2 QB 1, 2T/C3 B 4 1, 3D M1 R 12 G2 QC 1, 2T/C3 C 5 1, 3D M1 R 11 G2 QD 1, 2T/C3 D 6 1, 3D M1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
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SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056B – MARCH 1987 – REVISED AUGUST 2001 logic symbol, each flip-flop R TE R Q1 1, 2T/C3 CLK D Q1 G2 Q2 1, 3D Q2 LOAD M1 logic diagram, each flip-flop (positive logic) R TE (Toggle Enable) Q1 CLK Q2 D LOAD 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056B – MARCH 1987 – REVISED AUGUST 2001 typical clear, preset, count, and inhibit sequences The following timing sequence is illustrated below: 1. Clear outputs to zero 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4.
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SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056B – MARCH 1987 – REVISED AUGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.2 V to 7 V Input current range .
PAGE 7
SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056B – MARCH 1987 – REVISED AUGUST 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C fclock Clock frequency CLK high or low (loading) tw Pulse duration CLK (counting) tsu ENP and ENT before CLK↑ Data after CLK↑ th Hold time LOAD after CLK↑ ENP and ENT after CLK↑ tsu Inactive-state setup time, CLR high before CLK↑† † Inactive-state setup time also is refer
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SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056B – MARCH 1987 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL (see Note A) From Output Under Test CL (see Note A) Test Point 500 Ω 7V Open 500 Ω S1 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Collector Open 7V Open 7V LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74F161ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74F161ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74F161ADR SN74F161ANSR SOIC D 16 2500 333.2 345.9 28.6 SO NS 16 2000 367.0 367.0 38.
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