Datasheet

SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B – MARCH 1987 – REVISED MAY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
description
These devices contain four independent 2-input
OR gates. They perform the Boolean functions
Y = A + B or Y = A
• B in positive logic.
The SN54F32 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F32 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A B
Y
H X H
X HH
LL L
logic symbol
†
1
1A
2
1B
4
2A
5
2B
9
3A
10
3B
12
4A
13
4B
1Y
3
2Y
6
3Y
8
4Y
11
≥1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram, each gate (positive logic)
A
B
Y
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54F32 ...J PACKAGE
SN74F32 ...D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
SN54F32 . . . FK PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
1B 1A NC
3Y 3A
V 4B
2Y
GND
NC
CC
NC – No internal connection
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.