Datasheet

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SN74F377A

OCTAL D-TYPE FLIP-FLOP

WITH CLOCK ENABLE

SDFS018D – D2932, MARCH 1987 – REVISED OCTOBER 1993

2–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• Contains Eight D-Type Flip-Flops

With Single-Rail Outputs

• Clock Enable Latched to Avoid False

Clocking

• Applications Include:

Buffer/Storage Registers

Shift Registers

Pattern Generators

• Buffered Common Enable Input

• Package Options Include Plastic

Small-Outline Packages and Standard

Plastic 300-mil DIPs

description

The SN74F377A is a monolithic, positive-edge-triggered, octal, D-type flip-flop with clock enable inputs. The

SN74F377A features a latched clock enable (CE

) input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the

positive-going edge of the clock pulse if CE

is low. Clock triggering occurs at a particular voltage level and is

not directly related to the positive-going pulse. When the clock input is at either the high or low level, the D input

signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the CE

input.

The SN74F377A is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CE CLK D

H X X Q

L ↑ HH

L↑LL

XLXQ

GND

CLK

DW OR N PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (11 pages)

PAGE 1
SN74F377A OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SDFS018D – D2932, MARCH 1987 – REVISED OCTOBER 1993 • • • • • DW OR N PACKAGE (TOP VIEW) Contains Eight D-Type Flip-Flops With Single-Rail Outputs Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Buffered Common Enable Input Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs CE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 20 2 19 3 18 4 17 5 16
PAGE 2
SN74F377A OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SDFS018D – D2932, MARCH 1987 – REVISED OCTOBER 1993 logic symbol† CE CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 11 3 G1 1C2 2 2D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 3
SN74F377A OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SDFS018D – D2932, MARCH 1987 – REVISED OCTOBER 1993 recommended operating conditions VCC VIH Supply voltage VIL IIK Low-level input voltage IOH IOL High-level output current Low-level output current TA Operating free-air temperature High-level input voltage MIN NOM MAX 4.5 5 5.5 2 UNIT V V Input clamp current 0.
PAGE 4
SN74F377A OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SDFS018D – D2932, MARCH 1987 – REVISED OCTOBER 1993 switching characteristics (see Note 4) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C MIN TYP 110 125 VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX † MAX MIN 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX 110 4 6.5 8.
PAGE 5
PACKAGE OPTION ADDENDUM www.ti.
PAGE 6
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74F377ADWR Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 2.7 12.0 24.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74F377ADWR SOIC DW 20 2000 367.0 367.0 45.
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