Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Receiver, transceiver SOIC 24

T/R

ODD/EVEN

ERR

GND

PARITY

DW OR NT PACKAGE

(TOP VIEW)

SN74F657

OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER

AND 3-STATE OUTPUTS

SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993

2–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• Combines ′F245 and ′F280B Functions in

One Package

• High-Impedance N-P-N Inputs for Reduced

Loading (70 µA in Low and High States)

• High Output Drive and Light Bus Loading

• 3-State B Outputs Sink 64 mA and Source

15 mA

• Input Diodes for Termination Effects

• Package Options Include Plastic

Small-Outline Packages and Standard

Plastic 300-mil DIPs

description

The SN74F657 contains eight noninverting

buffers with 3-state outputs and an 8-bit parity

generator/checker. It is intended for bus-oriented

applications. The buffers have a specified current

sinking capability of 24 mA at the A port and 64 mA

at the B port.

The transmit/receive (T/R

) input determines the direction of the data flow through the bidirectional transceivers.

When T/R

is high, data is transmitted from the A port to the B port. When T/R is low, data is received at the A port

from the B port.

When the output enable (OE

) input is high, both the A and B ports are placed in a high-impedance state

(disabled). The ODD/EVEN

input allows the user to select between odd or even parity systems. When

transmitting from A port to B port (T/R

high), PARITY is an output from the generator/checker. When receiving

from B port to A port (T/R

low), PARITY is an input.

When transmitting (T/R

high), the parity select (ODD/EVEN) input is made high or low as appropriate. The A port

is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by

ODD/EVEN

and the number of high bits on A port. When ODD/EVEN is low (for even parity) and the number

of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port

is even, the PARITY will be low, keeping even parity.

When in the receive mode (T/R

low), the B port is polled to determine the number of high bits. If ODD/EVEN

is low (for even parity) and the number of highs on B port is:

1. Odd and the PARITY input is high, then ERR

will be high signifying no error.

2. Even and the PARITY input is high, then ERR

will be low indicating an error.

The SN74F657 is characterized for operation from 0°C to 70°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (11 pages)

PAGE 1
SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993 • • • • • • Combines ′F245 and ′F280B Functions in One Package High-Impedance N-P-N Inputs for Reduced Loading (70 µA in Low and High States) High Output Drive and Light Bus Loading 3-State B Outputs Sink 64 mA and Source 15 mA Input Diodes for Termination Effects Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description DW OR NT PA
PAGE 2
SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993 FUNCTION TABLE NUMBER OF A OR B INPUTS THAT ARE HIGH 0 2, 0, 2 4, 4 6, 6 8 1 3 1, 3, 5 5, 7 Don’t care INPUTS OUTPUTS OE T/R ODD/EVEN INPUT/OUTPUT PARITY ERR OUTPUT MODE L H H H Z Transmit L H L L Z Transmit L L H H H Receive L L H L L Receive L L L H L Receive L L L L H Receive L H H L Z Transmit L H L H Z Transmit L
PAGE 3
SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993 logic diagram (positive logic) T/R 1 OE A1 24 2 23 3 22 4 21 5 20 6 17 8 16 9 15 10 14 A2 A3 A4 A5 A6 A7 A8 ODD/EVEN B1 B2 B3 B4 B5 B6 B7 B8 13 11 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARITY ERR 2–3
PAGE 4
SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (excluding I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.
PAGE 5
SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK Any output VOH B1 – B8, PARITY, ERR Any output TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = – 18 mA IOH = – 3 mA VCC = 4.5 V, VCC = 4.75 V, IOH = – 15 mA IOH = – 1 mA to – 3 mA A1 – A8 VOL B1 – B8, PARITY, ERR T/R II 45V VCC = 4.
PAGE 6
SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993 switching characteristics (see Note 2) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL A PARITY tPLH tPHL ODD/EVEN PARITY ERR PARITY, tPLH tPHL B ERR tPLH tPHL PARITY ERR tPZH tPZL OE A B A, B, PARITY PARITY, or ERR‡ tPHZ tPLZ OE A B A, B, PARITY PARITY, or ERR‡ VCC = 5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = 25°C VCC = 4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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