Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Preset/reset Differential SOIC 14

SN54F74, SN74F74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SDFS046A – MARCH 1987 – REVISED OCTOBER 1993

2–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• Package Options Include Plastic

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and Ceramic

300-mil DIPs

description

These devices contain two independent positive-

edge-triggered D-type flip-flops. A low level at the

preset (PRE

) or clear (CLR) inputs sets or resets

the outputs regardless of the levels of the other

inputs. When PRE

and CLR are inactive (high),

data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the

positive-going edge of the clock pulse. Clock

triggering occurs at a voltage level and is not

directly related to the rise time of the clock pulse.

Following the hold-time interval, data at the

D input may be changed without affecting the

levels at the outputs.

The SN54F74 is characterized for operation over

the full military temperature range of –55°C to

125°C. The SN74F74 is characterized for

operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE CLR CLK D Q Q

L H X X H L

H LXXLH

LLXXH

†

HH↑HHL

HH↑LLH

HHLXQ

†

The output levels are not guaranteed to meet the

minimum levels for V

. Furthermore, this

configuration is nonstable; that is, it will not persist

when PRE

or CLR returns to its inactive (high)

level.

SN54F74 ...J PACKAGE

SN74F74 ...D OR N PACKAGE

(TOP VIEW)

SN54F74 . . . FK PACKAGE

(TOP VIEW)

3212019

910111213

2CLK

2PRE

1CLK

1PRE

1CLR

2CLR

GND

NC – No internal connection

1CLR

1CLK

1PRE

GND

2CLR

2CLK

2PRE

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (17 pages)

PAGE 1
SN54F74, SN74F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SDFS046A – MARCH 1987 – REVISED OCTOBER 1993 • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs SN54F74 . . . J PACKAGE SN74F74 . . . D OR N PACKAGE (TOP VIEW) 1CLR 1D 1CLK 1PRE 1Q 1Q GND description 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54F74 . . .
PAGE 2
SN54F74, SN74F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SDFS046A – MARCH 1987 – REVISED OCTOBER 1993 logic symbol† 4 1PRE 1CLK 1D 1 1CLR 6 9 11 2CLK 1Q R 10 2PRE 1Q C1 2 1D 5 S 3 2Q 12 2D 8 13 2CLR 2Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.
PAGE 3
SN54F74, SN74F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SDFS046A – MARCH 1987 – REVISED OCTOBER 1993 recommended operating conditions SN54F74 VCC VIH Supply voltage VIL IIK Low-level input voltage IOH IOL High-level output current TA Operating free-air temperature High-level input voltage SN74F74 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 Input clamp current Low-level output current V V 0.8 0.
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SN54F74, SN74F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SDFS046A – MARCH 1987 – REVISED OCTOBER 1993 switching characteristics (see Note 3) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† ′F74 SN54F74 SN74F74 MIN MIN MIN TYP 100 145 3 4.9 6.8 3.8 8.5 3 7.8 3.6 5.8 8 4.4 10.5 3.6 9.2 2.4 4.2 6.1 3.2 8 2.4 PRE or CLR Q or Q tPHL 2.7 6.6 9 3.5 11.5 2.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74F74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74F74NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74F74DR SN74F74NSR SOIC D 14 2500 367.0 367.0 38.0 SO NS 14 2000 367.0 367.0 38.
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