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QFN PACKAGE

(TOP VIEW)

GND

REF

terminal 1

index area

GND

REF

PW PACKAGE

(TOP VIEW)

SN74GTL2003

www.ti.com

SCDS305A –FEBRUARY 2011–REVISED MARCH 2013

8-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR

Check for Samples: SN74GTL2003

FEATURES

APPLICATIONS

• Provides Bidirectional Voltage Translation • Bidirectional or Unidirectional Applications

With No Direction Control Required Requiring Voltage-Level Translation From Any

Voltage (0.95 V to 5 V) to Any Voltage (0.95 V

• Allows Voltage Level Translation From 0.95 V

to 5 V)

up to 5 V

• Low Voltage Processor I2C Port Translation to

• Provides Direct Interface With GTL, GTL+,

3.3-V and/or 5-V I2C Bus Signal Levels

LVTTL/TTL, and 5-V CMOS Levels

• GTL/GTL+ Translation to LVTTL/TTL Signal

• Low On-State Resistance Between Input and

Levels

Output Pins (Sn/Dn)

• Supports Hot Insertion

• No Power Supply Required – Will Not Latch Up

• 5-V-Tolerant Inputs

• Low Standby Current

• Flow-Through Pinout for Ease of Printed

Circuit Board Trace Routing

• ESD Performance Tested Per JESD 22

– 2000-V Human-Body Model

(A114-B, Class II)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The SN74GTL2003 provides eight NMOS pass transistors (Sn and Dn) with a common gate (G

REF

) and a

reference transistor (S

REF

and D

REF

). The low ON-state resistance of the switch allows connections to be made

with minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage

translations any voltage (0.95 V to 5 V) to any voltage (0.95 V to 5 V).

When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between

the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on

the Sn port is limited to the voltage set by the reference transistor (S

REF

). When the Sn port is HIGH, the Dn port

is pulled to VCC by the pullup resistors.

All transistors in the SN74GTL2003 have the same electrical characteristics, and there is minimal deviation from

one output to another in voltage or propagation delay. This offers superior matching over discrete transistor

voltage-translation solutions where the fabrication of the transistors is not symmetrical. With all transistors being

identical, the reference transistor (S

REF

) can be located on any of the other eight matched Sn/Dn

transistors, allowing for easier board layout. The translator transistors with integrated ESD circuitry provides

excellent ESD protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (21 pages)

PAGE 1
SN74GTL2003 www.ti.
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SN74GTL2003 SCDS305A – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com ORDERING INFORMATION VQFN – RKS –40°C to 85°C (1) ORDERABLE PART NUMBER PACKAGE (1) TA TSSOP – PW TOP-SIDE MARKING Tape and reel SN74GTL2003RKSR GK2003 Tube SN74GTL2003PW GK2003 Tape and reel SN74GTL2003PWR GK2003 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DESCRIPTION Table 1. PIN DESCRIPTION 2 PIN NO.
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SN74GTL2003 www.ti.com SCDS305A – FEBRUARY 2011 – REVISED MARCH 2013 FUNCTION TABLES Table 2. HIGH-to-LOW Translation (Assuming Dn is at the Higher Voltage Level) (1) (1) (2) (3) (4) (5) GREF (2) DREF H H 0V H H VTT (3) H H VTT L L 0 – VTT INPUTS D8–D1 SREF OUTPUT S8–S1 TRANSISTOR X X Off H VTT (4) On L L (5) On X X Off H = HIGH voltage level, L = LOW voltage level, X = don't care. GREF should be at least 1.5 V higher than SREF for best translator operation.
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SN74GTL2003 SCDS305A – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) (3) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VSREF DC source reference voltage –0.5 7 V VDREF DC drain reference voltage –0.5 7 V VGREF DC gate reference voltage –0.5 7 V VSn DC voltage port Sn –0.
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SN74GTL2003 www.ti.com SCDS305A – FEBRUARY 2011 – REVISED MARCH 2013 Electrical Characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP (1) MAX UNIT 260 350 mV VOL Low-level output voltage VDD = 3 V, VSREF = 1.365 V, VSn or VDn = 0.175 V, Iclamp = 15.2 mA VIK Input clamp voltage II = –18 mA VGREF = 0 V –1.
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SN74GTL2003 SCDS305A – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com AC Characteristics for Translator-Type Applications (1) VREF = 1.365 V to 1.635 V, VDD1 = 3 V to 3.6 V, VDD2 = 2.36 V to 2.64 V, GND = 0 V, tr = tf ≤ 3 ns, Tamb = –40°C to 85°C (see Figure 6) PARAMETER tPLH (1) (2) (3) (3) Propagation delay (Sn to Dn, Dn to Sn) MIN TYP (2) MAX 0.5 1.5 5.5 UNIT ns CON(max) of 30 pF and a COFF(max) of 15 pF is specified by design. All typical values are measured at VDD1 = 3.3 V, VDD2 = 2.
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SN74GTL2003 www.ti.com SCDS305A – FEBRUARY 2011 – REVISED MARCH 2013 AC Characteristics for Translator-Type Applications GND = 0 V, tR, CL = 50 pF, GREF = 5 V ± 0.5 V, Tamb = –40°C to 85°C PARAMETER tpd (1) Propagation delay MIN (1) MAX UNIT 250 ps This parameter is warranted but not production tested.
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SN74GTL2003 SCDS305A – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION Bidirectional Translation For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the GREF input must be connected to DREF and both pins pulled to HIGH-side VCC through a pullup resistor (typically 200 kW). A filter capacitor on DREF is recommended.
PAGE 9
SN74GTL2003 www.ti.com SCDS305A – FEBRUARY 2011 – REVISED MARCH 2013 VDPU = 5 V 200K Ω VREF = 1.8V GTL2003 GREF RPU RPU RPU DREF SREF RPU S1 D1 SW CPU I/O Chipset I/O S2 D2 SW VDPU = 3.3V RPU S7 RPU D7 Chipset I/O S8 D8 GND Figure 6.
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SN74GTL2003 SCDS305A – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Unidirectional Down Translation For unidirectional clamping (higher voltage to lower voltage), the GREF input must be connected to DREF and both pins pulled to the higher-side VCC through a pullup resistor (typically 200 kW). A filter capacitor on DREF is recommended. Pullup resistors are required if the chipset I/Os are open drain.
PAGE 11
SN74GTL2003 www.ti.com SCDS305A – FEBRUARY 2011 – REVISED MARCH 2013 Unidirectional Up Translation For unidirectional up translation (lower voltage to higher voltage), the reference transistor is connected the same as for a down translation. A pullup resistor is required on the higher voltage side (Dn or Sn) to get the full HIGH level, since the GTL device only passes the reference source (SREF) voltage as a HIGH when doing an up translation.
PAGE 12
SN74GTL2003 SCDS305A – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Sizing Pullup Resistors The pullup resistor value should limit the current through the pass transistor when it is in the on state to about 15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage also is higher in the on state. To set the current through each pass transistor at 15 mA, the pullup resistor value is calculated as: Pullup voltage (V ) - 0.
PAGE 13
SN74GTL2003 www.ti.com SCDS305A – FEBRUARY 2011 – REVISED MARCH 2013 REVISION HISTORY Changes from Original (February 2011) to Revision A • Page Updated voltage level transition from 1 V to 0.95 V. ............................................................................................................
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74GTL2003PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74GTL2003RKSR VQFN RKS 20 3000 177.8 12.4 2.73 4.85 1.03 4.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74GTL2003PWR SN74GTL2003RKSR TSSOP PW 20 2000 367.0 367.0 38.0 VQFN RKS 20 3000 202.0 201.0 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.