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FEATURES

DGV, DW, OR PW PACKAGE

(TOP VIEW)

GND

DIR

REF

GND

DESCRIPTION/ORDERING INFORMATION

SN74GTLPH306

8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER

SCES284E – OCTOBER 1999 – REVISED APRIL 2005

• TI-OPC™ Circuitry Limits Ringing on

Unevenly Loaded Backplanes

• OEC™ Circuitry Improves Signal Integrity and

Reduces Electromagnetic Interference

• Bidirectional Interface Between GTLP Signal

Levels and LVTTL Logic Levels

• LVTTL Interfaces Are 5-V Tolerant

• Medium-Drive GTLP Outputs (50 mA)

• LVTTL Outputs (–24 mA/24 mA)

• GTLP Rise and Fall Times Designed for

Optimal Data-Transfer Rate and Signal

Integrity in Distributed Loads

• I

off

and Power-Up 3-State Support Hot

Insertion

• Bus Hold on A-Port Data Inputs

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

The SN74GTLPH306 is a medium-drive, 8-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL

signal-level translation. The device provides a high-speed interface between cards operating at LVTTL logic

levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard

LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input

threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and

TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models.

The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance

down to 19 Ω .

GTLP is the Texas Instruments ( TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD

8-3. The ac specification of the SN74GTLPH306 is given only at the preferred higher-noise-margin GTLP, but the

user has the flexibility of using this device at either GTL (V

= 1.2 V and V

REF

= 0.8 V) or GTLP (V

= 1.5 V and

REF

= 1 V) signal levels.

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,

but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V

REF

is the B-port differential input

reference voltage.

This device is fully specified for hot-insertion applications using I

off

and power-up 3-state. The I

off

circuitry

disables the outputs, preventing damaging current backflow through the device when it is powered down. The

power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI-OPC, OEC, TI are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

PAGE 1
SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.
PAGE 2
SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E – OCTOBER 1999 – REVISED APRIL 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
PAGE 3
SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E – OCTOBER 1999 – REVISED APRIL 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 24 DIR 1 OE A1 22 3 B1 23 VREF To Seven Other Channels Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX –0.5 4.6 A port and control inputs –0.5 7 B port and VREF –0.5 4.6 A port –0.5 7 B port –0.5 4.
PAGE 4
SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.
PAGE 5
SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E – OCTOBER 1999 – REVISED APRIL 2005 Electrical Characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port VCC = 3.15 V, II = –18 mA VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC – 0.2 IOH = –12 mA 2.4 IOH = –24 mA 2 VCC = 3.15 V VCC = 3.15 V to 3.45 V, A port VOL B port A-port and control inputs II (2) MIN TYP (1) MAX TEST CONDITIONS VCC = 3.15 V VCC = 3.
PAGE 6
SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E – OCTOBER 1999 – REVISED APRIL 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) PARAMETER tPLH tPHL ten tdis tr A B OE B MIN TYP (1) MAX 1 7.5 1 7.5 1 8 1 8 UNIT ns ns Rise time, B outputs (20% to 80%) 2.2 ns tf Fall time, B outputs (80% to 20%) 2.1 ns Rise time, A outputs (10% to 90%) 4.
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SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E – OCTOBER 1999 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 1.5 V 6V Open GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω 25 Ω From Output Under Test CL = 30 pF (see Note A) S1 Open 6V GND Test Point LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS 3V 1.5 V Input 1.
PAGE 8
SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E – OCTOBER 1999 – REVISED APRIL 2005 Distributed-Load Backplane Switching Characteristics The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical representation is shown in Figure 2.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74GTLPH306DGVR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74GTLPH306DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 SN74GTLPH306PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74GTLPH306DGVR TVSOP DGV 24 2000 346.0 346.0 29.0 SN74GTLPH306DWR SOIC DW 24 2000 346.0 346.0 41.0 SN74GTLPH306PWR TSSOP PW 24 2000 346.0 346.0 33.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.