Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74HC TSSOP 14

 

   

SCLS181E − DECEMBER 1982 − REVISED AUGUST 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 20-µA Max I

D Typical t

= 8 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

GND

SN54HC00 ...J OR W PACKAGE

SN74HC00 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

GND

SN54HC00 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

description/ordering information

The ’HC00 devices contain four independent 2-input NAND gates. They perform the Boolean function

Y = A

• B or Y = A + B in positive logic.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC00N SN74HC00N

Tube of 50 SN74HC00D

SOIC − D

Reel of 2500 SN74HC00DR

HC00

SOIC − D

Reel of 250 SN74HC00DT

HC00

−40°C to 85°C

SOP − NS Reel of 2000 SN74HC00NSR HC00

−40 C to 85 C

SSOP − DB Reel of 2000 SN74HC00DBR HC00

Tube of 90 SN74HC00PW

TSSOP − PW

Reel of 2000 SN74HC00PWR

HC00

TSSOP − PW

Reel of 250 SN74HC00PWT

HC00

CDIP − J Tube of 25 SNJ54HC00J SNJ54HC00J

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC00W SNJ54HC00W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HC00FK SNJ54HC00FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (21 pages)

PAGE 1
SCLS181E − DECEMBER 1982 − REVISED AUGUST 2003 D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC SN54HC00 . . . J OR W PACKAGE SN74HC00 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1B 1A NC VCC 4B SN54HC00 . . .
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SCLS181E − DECEMBER 1982 − REVISED AUGUST 2003 FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H H L L X H X L H logic diagram (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
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SCLS181E − DECEMBER 1982 − REVISED AUGUST 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 µA VOH VI = VIH or VIL IOH = −4 mA IOH = −5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC VI = VCC or 0 VI = VCC or 0, IO = 0 VCC MIN TA = 25°C TYP MAX SN74HC00 MIN MIN MAX 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.
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SCLS181E − DECEMBER 1982 − REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Input VCC 50% 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 50% 10% tPHL 90% 90% tr Input 50% 10% 90% 90% tr VCC 50% 10% 0 V tPHL Out-of-Phase Output 90% tf VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORM IN
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC00DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74HC00DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC00DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC00DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74HC00DR SOIC D 14 2500 333.2 345.9 28.6 SN74HC00DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC00DRG4 SOIC D 14 2500 333.2 345.9 28.6 SN74HC00DT SOIC D 14 250 367.0 367.0 38.0 SN74HC00PWR TSSOP PW 14 2000 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 21
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.