Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74HC SOIC 14

 

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  

SCLS077E − MARCH 1984 − REVISED NOVEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 20-µA Max I

D Typical t

= 8 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

GND

SN54HC03 ...J OR W PACKAGE

SN74HC03 . . . D, N, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

GND

SN54HC03 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

description/ordering information

The ’HC03 devices contain four independent 2-input NAND gates. They perform the Boolean function

Y = A

• B or Y = A + B in positive logic. The open-drain outputs require pullup resistors to perform correctly. They

may be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND

functions.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC03N SN74HC03N

Tube of 50 SN74HC03D

SOIC − D

Reel of 2500 SN74HC03DR

HC03

−40°C to 85°C

SOIC − D

Reel of 250 SN74HC03DT

HC03

−40 C to 85 C

SOP − NS Reel of 2000 SN74HC03NSR HC03

TSSOP − PW

Tube of 90 SN74HC03PW

HC03

TSSOP − PW

Reel of 2000 SN74HC03PWR

HC03

CDIP − J Tube of 25 SNJ54HC03J SNJ54HC03J

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC03W SNJ54HC03W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HC03FK SNJ54HC03FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (18 pages)

PAGE 1
SCLS077E − MARCH 1984 − REVISED NOVEMBER 2003 D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1Y NC 2A NC 2B 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 1A 1B 1Y 2A 2B 2Y GND SN54HC03 . . .
PAGE 2
SCLS077E − MARCH 1984 − REVISED NOVEMBER 2003 FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H H L L X H X L H logic diagram (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 3
SCLS077E − MARCH 1984 − REVISED NOVEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH VOL II ICC TEST CONDITIONS VI = VIH or VIL, VCC VO = VCC TA = 25°C TYP MAX SN54HC03 SN74HC03 MIN MIN MAX MAX UNIT µA 6V 0.01 0.5 10 5 2V 0.002 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 IOL = 4 mA IOL = 5.
PAGE 4
SCLS077E − MARCH 1984 − REVISED NOVEMBER 2003 PARAMETER MEASUREMENT INFORMATION VCC RL = 1 kΩ From Output Under Test VCC Test Point Input 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT Input 50% 10% 90% VCC 50% 10% 0 V 90% tr 50% tPHL 90% 10% tPHL Out-of-Phase Output 90% tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES tPLH 50% 10% 10% VOH 50% 10% V OL tf VOH VOL tf VOLTAGE WAVEFORMS PROPAGA
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74HC03DR Package Package Pins Type Drawing SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC03DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC03PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC03DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC03DT SOIC D 14 250 367.0 367.0 38.0 SN74HC03PWR TSSOP PW 14 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.