Datasheet

 
 

    
SCLS470A − MARCH 2003 − REVISED OCTOBER 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Wide Operating Voltage Range of 2 V to 6 V
D Low Input Current of 1 µA Max
D High-Current Outputs Drive Up To
10 LSTTL Loads
D Low Power Consumption, 40-µA Max I
CC
D Typical t
pd
= 12 ns
D ±4-mA Output Drive at 5 V
SN54HC109 ...J OR W PACKAGE
SN74HC109 . . . D, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1CLR
1J
1K
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2J
2K
2CLK
2PRE
2Q
2Q
SN54HC109 . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2J
2K
NC
2CLK
2PRE
1K
1CLK
NC
1PRE
1Q
1J
1CLR
NC
2Q
2Q
V
2CLR
1Q
GND
NC
CC
description/ordering information
These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE)
or clear (CLR
) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR
are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs
on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related
directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K
inputs can be
changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by
grounding K
and tying J high. They also can perform as D-type flip-flops if J and K are tied together.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N Tube of 25 SN74HC109N SN74HC109N
Tube of 40 SN74HC109D
−40°C to 85°C SOIC − D
Reel of 2500 SN74HC109DR
HC109
−40 C to 85 C
SOIC − D
Reel of 250 SN74HC109DT
HC109
SOP − NS Reel of 2000 SN74HC109NSR HC109
CDIP − J Tube of 25 SNJ54HC109J SNJ54HC109J
−55°C to 125°C
CFP − W Tube of 150 SNJ54HC109W SNJ54HC109W
−55 C to 125 C
LCCC − FK Tube of 55 SNJ54HC109FK SNJ54HC109FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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