Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Preset/reset Differential SOIC 16

 

   

   

SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 40-µA Max I

D Typical t

= 13 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

description/ordering information

The ’HC112 devices contain two independent J-K

negative-edge-triggered flip-flops. A low level at

the preset (PRE

) or clear (CLR) inputs sets or

resets the outputs, regardless of the levels of the

other inputs. When PRE

and CLR are inactive

(high), data at the J and K inputs meeting the

setup time requirements are transferred to the

outputs on the negative-going edge of the clock

(CLK) pulse. Clock triggering occurs at a voltage

level and is not directly related to the fall time of the

CLK pulse. Following the hold-time interval, data

at the J and K inputs may be changed without

affecting the levels at the outputs. These versatile

flip-flops perform as toggle flip-flops by tying J and

K high.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC112N SN74HC112N

−40°C to 85°C

Tube of 40 SN74HC112D

−40°C to 85°C

SOIC − D

Reel of 2500 SN74HC112DR

HC112

SOIC − D

Reel of 250 SN74HC112DT

HC112

CDIP − J Tube of 25 SNJ54HC112J SNJ54HC112J

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC112W SNJ54HC112W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HC112FK SNJ54HC112FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

3212019

910111213

2CLR

2CLK

1PRE

1CLK

2Q V

1CLR

GND

SN54HC112 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

1CLK

1PRE

GND

1CLR

2CLR

2CLK

2PRE

SN54HC112 ...J OR W PACKAGE

SN74HC112 ...D OR N PACKAGE

(TOP VIEW)

2PRE

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Summary of content (18 pages)

PAGE 1
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 SN54HC112 . . . J OR W PACKAGE SN74HC112 . . .
PAGE 2
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 FUNCTION TABLE OUTPUTS INPUTS PRE CLR CLK L H X H L X J K Q Q X X H L X X H H† L L X X X L H† H H ↓ L L Q0 Q0 H H ↓ H L H L H H ↓ L H L H H ↓ H H H Toggle H H H X X Q0 Q0 † This configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level.
PAGE 3
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 µA VOH IOL = 20 µA VI = VCC or 0 VI = VCC or 0, TA = 25°C TYP MAX MIN MAX SN74HC112 MIN 2V 1.9 1.998 1.9 1.9 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.
PAGE 5
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax PRE or CLR Q or Q tpd CLK tt Q or Q Q or Q VCC MIN TA = 25°C TYP MAX SN54HC112 MIN MAX SN74HC112 MIN 2V 5 10 3.4 4 4.
PAGE 6
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% 50% 10%
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74HC112DR Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.5 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC112DR SOIC D 16 2500 333.2 345.9 28.
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