Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74HC TSSOP 14

 

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  

SCLS034F − DECEMBER 1982 − REVISED NOVEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 20-µA Max I

D Typical t

= 14 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D Operation From Very Slow Input

Transitions

D Temperature-Compensated Threshold

Levels

D High Noise Immunity

D Same Pinouts as ’HC00

description/ordering information

Each circuit functions as a NAND gate, but

because of the Schmitt action, it has different input

threshold levels for positive- and negative-going

signals. The ’HC132 devices perform the Boolean

function Y = A

• B or Y = A + B in positive logic.

These circuits are temperature compensated and

can be triggered from the slowest of input ramps

and still give clean jitter-free output signals.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC132N SN74HC132N

Tube of 50 SN74HC132D

SOIC − D

Reel of 2500 SN74HC132DR

HC132

SOIC − D

Reel of 250 SN74HC132DT

HC132

−40°C to 85°C

SOP − NS Reel of 2000 SN74HC132NSR HC132

−40 C to 85 C

SSOP − DB Reel of 2000 SN74HC132DBR HC132

Tube of 90 SN74HC132PW

TSSOP − PW

Reel of 2000 SN74HC132PWR

HC132

TSSOP − PW

Reel of 250 SN74HC132PWT

HC132

CDIP − J Tube of 25 SNJ54HC132J SNJ54HC132J

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC132W SNJ54HC132W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HC132FK SNJ54HC132FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

SN54HC132 ...J OR W PACKAGE

SN74HC132 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

GND

SN54HC132 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

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Summary of content (21 pages)

PAGE 1
SCLS034F − DECEMBER 1982 − REVISED NOVEMBER 2004 D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 20-µA Max ICC Typical tpd = 14 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as ’HC00 SN54HC132 . . . J OR W PACKAGE SN74HC132 . . .
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SCLS034F − DECEMBER 1982 − REVISED NOVEMBER 2004 FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H H L L X H X L H logic diagram (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
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SCLS034F − DECEMBER 1982 − REVISED NOVEMBER 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VT+ VT− MAX SN74HC132 MIN MAX 2V 0.7 1.2 1.5 0.7 1.5 0.7 1.5 4.5 V 1.55 2.5 3.15 1.55 3.15 1.55 3.15 6V 2.1 3.3 4.2 2.1 4.2 2.1 4.2 2V 0.3 0.6 1 0.3 1 0.3 1 4.5 V 0.9 1.6 2.45 0.9 2.45 0.9 2.45 6V 1.
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SCLS034F − DECEMBER 1982 − REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Input VCC 50% 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 50% 10% tPHL 90% 90% tr Input 50% 10% 90% 90% tr VCC 50% 10% 0 V tPHL Out-of-Phase Output 90% tf VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION T
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC132DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74HC132DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC132DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC132DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74HC132DR SOIC D 14 2500 333.2 345.9 28.6 SN74HC132DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC132DT SOIC D 14 250 367.0 367.0 38.0 SN74HC132PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74HC132PWT TSSOP PW 14 250 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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