Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Demultiplexer, decoder Decoder/demultiplexer Single supply SSOP 16

SN54HC138, SN74HC138

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Targeted Specifically for High-Speed

Memory Decoders and Data-Transmission

Systems

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 80-μA Max I

D Typical t

= 15 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 μA Max

D Incorporate Three Enable Inputs to Simplify

Cascading and/or Data Reception

description/ordering information

The ’HC138 devices are designed to be used in

high-performance memory-decoding or data-

routing applications requiring very short

propagation delay times. In high-performance

memory systems, these decoders can be used to

minimize the effects of system decoding. When

employed with high-speed memories utilizing a

fast enable circuit, the delay times of these

decoders and the enable time of the memory are

usually less than the typical access time of the

memory. This means that the effective system

delay introduced by the decoders is negligible.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC138N SN74HC138N

Tube of 40 SN74HC138D

SOIC − D

Reel of 2500 SN74HC138DR

HC138

SOIC

Reel of 250 SN74HC138DT

HC138

−40°C to 85°C

SOP − NS Reel of 2000 SN74HC138NSR HC138

40 C

85 C

SSOP − DB Reel of 2000 SN74HC138DBR HC138

Tube of 90 SN74HC138PW

TSSOP − PW

Reel of 2000 SN74HC138PWR

HC138

TSSOP

Reel of 250 SN74HC138PWT

HC138

CDIP − J Tube of 25 SNJ54HC138J SNJ54HC138J

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC138W SNJ54HC138W

55 C

125 C

LCCC − FK Tube of 55 SNJ54HC138FK SNJ54HC138FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

3212019

910111213

GND

SN54HC138 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

GND

SN54HC138 ...J OR W PACKAGE

SN74HC138 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (22 pages)

PAGE 1
SN54HC138, SN74HC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Targeted Specifically for High-Speed D D D D D D D Memory Decoders and Data-Transmission Systems Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-μA Max ICC Typical tpd = 15 ns ±4-mA Output Drive at 5 V Low Input Current of 1 μA Max Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception SN54HC138 . . .
PAGE 2
SN54HC138, SN74HC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003 description/ordering information (continued) The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter.
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SN54HC138, SN74HC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003 logic diagram (positive logic) 15 A B C 1 14 Y1 2 13 3 12 11 10 G1 Y0 6 Y2 Y3 Y4 Y5 9 Y6 G2A 4 7 G2B Y7 5 Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
SN54HC138, SN74HC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003 recommended operating conditions (see Note 3) SN54HC138 VCC Supply voltage VCC = 2 V VIH VCC = 4.5 V High-level High level input voltage VCC = 6 V MIN NOM MAX 2 5 6 Input voltage VO Output voltage TA 5 6 3.15 4.2 0 0 Input transition rise/fall time 2 4.2 VCC = 2 V Δt/Δv MAX 3.15 VCC = 6 V VI NOM 1.5 VCC = 4.5 V Low-level Low level input voltage MIN 1.
PAGE 5
SN54HC138, SN74HC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC A, B, or C Any Y tpd Enable Any Y tt Any y TA = 25°C MIN SN54HC138 MIN SN74HC138 TYP MAX MAX MIN MAX 2V 67 180 270 225 4.5 V 18 36 54 45 6V 15 31 46 38 2V 66 155 235 195 4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC138DBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74HC138DR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC138DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC138DBR SSOP DB 16 2000 367.0 367.0 38.0 SN74HC138DR SOIC D 16 2500 364.0 364.0 27.0 SN74HC138DRG4 SOIC D 16 2500 333.2 345.9 28.6 SN74HC138PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC138PWT TSSOP PW 16 250 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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