Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Binary counter 74HC Positive slope 36 MHz SOIC 16 N

 

   

SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Typical t

= 14 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D Internal Look-Ahead for Fast Counting

D Carry Output for n-Bit Cascading

D Synchronous Counting

D Synchronously Programmable

SN54HC161 ...J OR W PACKAGE

SN74HC161 . . . D, N, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

SN54HC161 . . . FK PACKAGE

(TOP VIEW)

CLK

CLR

LOAD

ENT

RCO

ENP

GND

CLR

CLK

ENP

GND

RCO

ENT

LOAD

NC − No internal connection

description/ordering information

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed

counting designs. The ’HC161 devices are 4-bit binary counters. Synchronous operation is provided by having

all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed

by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output

counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK)

input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC161N SN74HC161N

Tube of 40 SN74HC161D

SOIC − D

Reel of 2500 SN74HC161DR

HC161

−40°C to 85°C

SOIC − D

Reel of 250 SN74HC161DT

HC161

−40°C to 85°C

SOP − NS Reel of 2000 SN74HC161NSR HC161

Tube of 90 SN74HC161PW

TSSOP − PW

Reel of 2000 SN74HC161PWR

HC161

TSSOP − PW

Reel of 250 SN74HC161PWT

HC161

CDIP − J Tube of 25 SNJ54HC161J SNJ54HC161J

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC161W SNJ54HC161W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HC161FK SNJ54HC161FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (29 pages)

PAGE 1
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 14 ns ±4-mA Output Drive at 5 V 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 SN54HC161 . . .
PAGE 2
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 description/ordering information (continued) These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
PAGE 3
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 logic diagram (positive logic) LOAD ENT ENP 9 10 15 LD† 7 RCO CK† CLK CLR A B C D 2 1 CK LD R M1 G2 1, 2T/1C3 G4 3D 4R 3 M1 G2 1, 2T/1C3 G4 3D 4R 4 M1 G2 1, 2T/1C3 G4 3D 4R 5 M1 G2 1, 2T/1C3 G4 3D 4R 6 14 13 12 11 QA QB QC QD † For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram.
PAGE 4
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 logic symbol, each D/T flip-flop LD (Load) M1 TE (Toggle Enable) G2 CK (Clock) 1, 2T/1C3 G4 D (Inverted Data) 3D R (Inverted Reset) 4R Q (Output) logic diagram, each D/T flip-flop (positive logic) CK LD TE LD† TG TG LD† Q TG TG CK† D TG CK† R † The origins of LD and CK are shown in the logic diagram of the overall device.
PAGE 5
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 typical clear, preset, count, and inhibit sequence The following sequence is illustrated below: 1. Clear outputs to zero (asynchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4.
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SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 7
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 µA VOH IOL = 20 µA VOL II ICC VI = VCC or 0 VI = VCC or 0, TA = 25°C TYP MAX MIN MAX SN74HC161 MIN 1.9 1.998 1.9 1.9 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.
PAGE 8
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax RCO CLK tpd Any Q ENT RCO Any Q tPHL CLR RCO tt Any VCC MIN TA = 25°C TYP MAX SN54HC161 MIN MAX SN74HC161 MIN 2V 6 14 4.2 5 4.5 V 31 40 21 25 6V 36 44 25 29 MAX UNIT MHz 2V 83 215 325 270 4.
PAGE 9
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 50% 10% 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% tPHL Out-of-Phase Output 90
PAGE 10
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION n-bit synchronous counters This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit counter. The ’HC161 devices count in binary. Virtually any count mode (modulo-N, N1-to-N2, N1-to-maximum) can be used with this fast look-ahead circuit.
PAGE 11
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION LSB CTR CT=0 M1 3CT=MAX G3 CLR Clear (L) LOAD ENT Count (H)/ Disable (L) ENP CLK RCO G4 C5/2,3,4+ Load (L) A 1,5D [1] QA Count (H)/ Disable (L) B [2] QB C [3] QC Clock D [4] QD CTR CT=0 M1 3CT=MAX G3 CLR LOAD ENT ENP CLK RCO G4 C5/2,3,4+ A 1,5D [1] QA B [2] QB C [3] QC D [4] QD CTR CT=0 M1 3CT=MAX G3 CLR LOAD ENT ENP CLK RCO G4 C5/2,3,4+ A 1
PAGE 12
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION The glitch on RCO is caused because the propagation delay of the rising edge of QA of the second stage is shorter than the propagation delay of the falling edge of ENT. RCO is the product of ENT, QA, QB, QC, and QD (ENT × QA × QB × QC × QD). The resulting glitch is about 7−12 ns in duration. Figure 3 shows the condition in which the glitch occurs.
PAGE 13
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003 APPLICATION INFORMATION timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency TA = 25°C MIN MAX Pulse duration, CLK high or low MIN MAX SN74HC161 MIN MAX 2V 3.6 2.5 2.9 4.5 V 18 12 14 6V tw SN54HC161 21 14 UNIT MHz 17 2V 140 200 170 4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74HC161DR Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC161NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC161PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC161DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC161NSR SO NS 16 2000 367.0 367.0 38.0 SN74HC161PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC161PWT TSSOP PW 16 250 367.0 367.0 35.
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