Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register 74 HC 164 Shift register Push pull PDIP 14

SN54HC164, SN74HC164

8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

SCLS115E − DECEMBER 1982 − REVISED NOVEMBER 2010

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 80-μA Max I

D Typical t

= 20 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 μA Max

D AND-Gated (Enable/Disable) Serial Inputs

D Fully Buffered Clock and Serial Inputs

D Direct Clear

description/ordering information

These 8-bit shift registers feature AND-gated

serial inputs and an asynchronous clear (CLR

)

input. The gated serial (A and B) inputs permit

complete control over incoming data; a low at

either input inhibits entry of the new data and

resets the first flip-flop to the low level at the next

clock (CLK) pulse. A high-level input enables the

other input, which then determines the state of the

first flip-flop. Data at the serial inputs can be

changed while CLK is high or low, provided the

minimum setup time requirements are met.

Clocking occurs on the low-to-high-level transition

of CLK.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC164N SN74HC164N

Tube of 50 SN74HC164D

SOIC − D

Reel of 2500 SN74HC164DRG3

HC164

40°C to 85°C

SOIC D

Reel of 250 SN74HC164DT

HC164

−40°C to 85°C

SOP − NS Reel of 2000 SN74HC164NSR HC164

Tube of 90 SN74HC164PW

TSSOP − PW

Reel of 2000 SN74HC164PWR

HC164

TSSOP PW

Reel of 250 SN74HC164PWT

HC164

CDIP − J Tube of 25 SNJ54HC164J SNJ54HC164J

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC164W SNJ54HC164W

LCCC − FK Tube of 55 SNJ54HC164FK SNJ54HC164FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54HC164 ...J OR W PACKAGE

SN74HC164 . . . D, N, NS, OR PW PACKAGE

(TOP VIEW)

GND

CLR

CLK

3212019

910111213

CLK

CLR

GND

SN54HC164 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (21 pages)

PAGE 1
SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115E − DECEMBER 1982 − REVISED NOVEMBER 2010 D D D D D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-μA Max ICC Typical tpd = 20 ns ±4-mA Output Drive at 5 V Low Input Current of 1 μA Max AND-Gated (Enable / Disable) Serial Inputs Fully Buffered Clock and Serial Inputs Direct Clear SN54HC164 . . . J OR W PACKAGE SN74HC164 . . .
PAGE 2
SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115E − DECEMBER 1982 − REVISED NOVEMBER 2010 FUNCTION TABLE OUTPUTS INPUTS CLR CLK A B QA Q B . . .
PAGE 3
SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115E − DECEMBER 1982 − REVISED NOVEMBER 2010 typical clear, shift, and clear sequence Serial Inputs CLR A B CLK QA QB Outputs QC QD QE QF QG QH Clear Clear absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 4
SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115E − DECEMBER 1982 − REVISED NOVEMBER 2010 recommended operating conditions (see Note 3) SN54HC164 VCC Supply voltage VCC = 2 V VIH VCC = 4.5 V High-level High level input voltage VCC = 6 V MIN NOM MAX 2 5 6 Input voltage VO Output voltage TA 5 6 3.15 4.2 0 0 Input transition rise/fall time 2 4.2 VCC = 2 V Δt/Δv† MAX 3.15 VCC = 6 V VI NOM 1.5 VCC = 4.5 V Low-level Low level input voltage MIN 1.
PAGE 5
SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115E − DECEMBER 1982 − REVISED NOVEMBER 2010 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency CLR low tw Pulse duration CLK high or low Data tsu Setup time before CLK↑ CLR inactive th Hold time,, data after CLK↑ TA = 25°C MIN SN54HC164 MAX MIN MAX SN74HC164 MIN MAX 2V 6 4.2 5 4.5 V 31 21 25 6V 36 25 28 2V 100 150 125 4.
PAGE 6
SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115E − DECEMBER 1982 − REVISED NOVEMBER 2010 PARAMETER MEASUREMENT INFORMATION From Output Under Test High-Level Pulse Test Point 50% 50% VCC 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% LOAD CIRCUIT 50% 0V VOLTAGE WAVEFORMS PULSE DURATIONS Input 50% VCC 50% 0V tPLH Reference Input In-Phase Output 50% 10% 0V tsu Data Input 50% 10% VCC 50% 90% tr 90% 90% tr th 90% tPHL tPHL VCC Out-of-Phase Output
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 29-Aug-2012 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC164DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC164DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC164DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC164DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC164DR SOIC D 14 2500 333.2 345.9 28.6 SN74HC164DRG4 SOIC D 14 2500 333.2 345.9 28.6 SN74HC164DRG4 SOIC D 14 2500 367.0 367.0 38.0 SN74HC164DT SOIC D 14 250 367.0 367.0 38.0 SN74HC164NSR SO NS 14 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.