Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Shift register Differential TSSOP 16



   

SCLS473A − APRIL 2003 − REVISED JANUARY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

D Extended Temperature Performance of Up

To −55°C to 125°C

D Enhanced Diminishing Manufacturing

Sources (DMS) Support

D Enhanced Product-Change Notification

D Qualification Pedigree

†

D 2-V to 6-V V

Operation

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Typical t

= 13 ns

†

Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D Complementary Outputs

D Direct Overriding Load (Data) Inputs

D Gated Clock Inputs

D Parallel-to-Serial Data Conversion

description/ordering information

The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shifts the data toward a serial (Q

)

output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled

by a low level at the shift/load (SH/LD

) input. The SN74HC165 device also features a clock-inhibit (CLK INH)

function and a complementary serial (Q

) output.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD

is held high and CLK

INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high

transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK

is high. Parallel loading is inhibited when SH/LD

is held high. While SH/LD is low, the parallel inputs to the

ORDERING INFORMATION

PACKAGE

‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40°C to 125°C

SOIC − D Tape and reel SN74HC165QDREP HC165EP

−40°C to 125°C

TSSOP − PW Tape and reel SN74HC165QPWREP HC165EP

−55°C to 125°C SOIC − D Tape and reel SN74HC165MDREP HC165MEP

‡

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D OR PW PACKAGE

(TOP VIEW)

SH/LD

CLK

GND

CLK INH

SER

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Summary of content (16 pages)

PAGE 1
SCLS473A − APRIL 2003 − REVISED JANUARY 2004 D Controlled Baseline D D D D D D D D D D D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of Up To −55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† 2-V to 6-V VCC Operation Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 13 ns ±4-mA Output Drive at 5 V Low
PAGE 2
SCLS473A − APRIL 2003 − REVISED JANUARY 2004 FUNCTION TABLE INPUTS FUNCTION SH/LD CLK CLK INH L X X H H X No change H X H H L ↑ No change Shift† H ↑ L Shift† Parallel load † Shift = content of each internal register shifts toward serial output QH. Data at SER is shifted into the first register.
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SCLS473A − APRIL 2003 − REVISED JANUARY 2004 typical shift, load, and inhibit sequence CLK CLK INH SER L SH/LD Data Inputs A H B L C H D L E H F L G H H H QH H H L H L H L H QH L L H L H L H L Inhibit Serial Shift Load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
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SCLS473A − APRIL 2003 − REVISED JANUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SCLS473A − APRIL 2003 − REVISED JANUARY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 µA VOH VI = VIH or VIL IOH = −4 mA IOH = −5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC VI = VCC or 0 VI = VCC or 0, IO = 0 Ci VCC MIN MIN 2V 1.9 1.998 1.9 4.5 V 4.4 4.499 4.4 6V 5.9 5.999 5.9 4.5 V 3.98 4.3 3.7 6V 5.48 5.
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SCLS473A − APRIL 2003 − REVISED JANUARY 2004 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency SH/LD low tw Pulse duration CLK high or low SH/LD high before CLK↑ SER before CLK↑ tsu Setup time CLK INH low before CLK↑ CLK INH high before CLK↑ Data before SH/LD↓ SER data after CLK↑ th Hold time PAR data after SH/LD↓ 6 POST OFFICE BOX 655303 TA = 25°C MIN MAX MIN MAX 2V 6 4
PAGE 7
SCLS473A − APRIL 2003 − REVISED JANUARY 2004 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax SH/LD tpd QH or QH CLK QH or QH H QH or QH tt Any VCC MIN TA = 25°C TYP MAX MIN 2V 6 13 4.2 4.5 V 31 50 21 6V 36 62 25 MAX UNIT MHz 2V 80 150 225 4.5 V 20 30 45 6V 16 26 38 2V 75 150 225 4.
PAGE 8
SCLS473A − APRIL 2003 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% 50% 10% tPHL Out-of-Phase Output 90% VOLTAGE WAV
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC165QDREP SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC165QPWREP TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC165QDREP SOIC D 16 2500 333.2 345.9 28.6 SN74HC165QPWREP TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.