Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Master rest Differential TSSOP 16

 

  

 

SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Contain Four Flip-Flops With Double-Rail

Outputs

D Typical t

= 13 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D Applications Include:

− Buffer/Storage Registers

− Shift Registers

− Pattern Generators

SN54HC175 ...J OR W PACKAGE

SN74HC175 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

SN54HC175...FK PACKAGE

(TOP VIEW)

CLR

GND

CLK

3 2 1 20 19

910111213

CLR

CLK

GND

NC − No internal connection

description/ordering information

These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. The ’HC175 devices feature

complementary outputs from each flip-flop.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC175N SN74HC175N

Tube of 40 SN74HC175D

SOIC − D

Reel of 2500 SN74HC175DR

HC175

SOIC − D

Reel of 250 SN74HC175DT

HC175

−40°C to 85°C

SOP − NS Reel of 2000 SN74HC175NSR HC175

−40 C to 85 C

SSOP − DB Reel of 2000 SN74HC175DBR HC175

Tube of 90 SN74HC175PW

TSSOP − PW

Reel of 2000 SN74HC175PWR

HC175

TSSOP − PW

Reel of 250 SN74HC175PWT

HC175

CDIP − J Tube of 25 SNJ54HC175J SNJ54HC175J

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC175W SNJ54HC175W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HC175FK SNJ54HC175FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (22 pages)

PAGE 1
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003 D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Contain Four Flip-Flops With Double-Rail Outputs Typical tpd = 13 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Applications Include: − Buffer/Storage Registers − Shift Registers − Pattern Generators SN54HC175 . . .
PAGE 2
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003 description/ordering information (continued) Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going edge of CLK.
PAGE 3
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003 recommended operating conditions (see Note 3) SN54HC175 VCC Supply voltage VIH VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO Input voltage NOM MAX 2 5 6 NOM MAX 2 5 6 1.5 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition rise/fall time MIN 1.
PAGE 4
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency CLR low tw Pulse duration CLK high or low Data tsu Setup time before CLK↑ CLR inactive th CLK↑ Hold time, data after CLK TA = 25°C MIN MAX SN54HC175 MIN MAX SN74HC175 MIN MAX 2V 6 4.2 5 4.5 V 31 21 25 6V 36 25 29 2V 80 120 100 4.
PAGE 5
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 50% 10% 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% tPHL Out-of-Phase Output
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74HC175DBR SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 12.0 16.0 Q1 DB 16 2000 330.0 16.4 8.2 6.6 2.5 SN74HC175DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC175NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC175DBR SSOP DB 16 2000 367.0 367.0 38.0 SN74HC175DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC175NSR SO NS 16 2000 367.0 367.0 38.0 SN74HC175PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC175PWT TSSOP PW 16 250 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.