Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74HC PDIP 14

 

   

SCLS086F − DECEMBER 1982 − REVISED AUGUST 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 20-µA Max I

D Typical t

= 11 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

GND

SN54HC20 ...J OR W PACKAGE

SN74HC20 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

GND

SN54HC20 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

description/ordering information

The ’HC20 devices contain two independent 4-input NAND gates. They perform the Boolean function

Y = A

• B • C • D or Y = A + B + C + D in positive logic.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC20N SN74HC20N

Tube of 50 SN74HC20D

SOIC − D

Reel of 2500 SN74HC20DR

HC20

SOIC − D

Reel of 250 SN74HC20DT

HC20

−40°C to 85°C

SOP − NS Reel of 2000 SN74HC20NSR HC20

−40 C to 85 C

SSOP − DB Reel of 2000 SN74HC20DBR HC20

Tube of 90 SN74HC20PW

TSSOP − PW

Reel of 2000 SN74HC20PWR

HC20

TSSOP − PW

Reel of 250 SN74HC20PWT

HC20

CDIP − J Tube of 25 SNJ54HC20J SNJ54HC20J

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC20W SNJ54HC20W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HC20FK SNJ54HC20FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (21 pages)

PAGE 1
SCLS086F − DECEMBER 1982 − REVISED AUGUST 2003 D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC SN54HC20 . . . FK PACKAGE (TOP VIEW) 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2D 2C NC 2B 2A 2Y NC NC 1C NC 1D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2C NC NC NC 2B 1Y GND NC 2Y 2A 1 1B 1A NC VCC 2D SN54HC20 . . . J OR W PACKAGE SN74HC20 . . .
PAGE 2
SCLS086F − DECEMBER 1982 − REVISED AUGUST 2003 FUNCTION TABLE (each gate) INPUTS A B C D OUTPUT Y H H H H L L X X X H X L X X H X X L X H X X X L H logic diagram (positive logic) 1A 1B 1C 1D 1 2 4 5 6 2A 2B 2C 2D 1Y 9 10 12 13 8 2Y Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . .
PAGE 3
SCLS086F − DECEMBER 1982 − REVISED AUGUST 2003 recommended operating conditions (see Note 3) SN54HC20 VCC Supply voltage VIH VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO Input voltage NOM MAX 2 5 6 NOM MAX 2 5 6 1.5 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition rise/fall time MIN 1.5 0 Output voltage ∆t/∆v MIN VCC = 4.
PAGE 4
SCLS086F − DECEMBER 1982 − REVISED AUGUST 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) TA = 25°C TYP MAX SN54HC20 SN74HC20 MIN MIN PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V 45 110 165 140 tpd A, B, C, or D Y 4.5 V 14 22 33 28 6V 11 19 28 24 tt Y MIN MAX MAX 2V 27 75 110 95 4.
PAGE 5
SCLS086F − DECEMBER 1982 − REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Input VCC 50% 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 50% 10% tPHL 90% 90% tr Input 50% 10% 90% 90% tr VCC 50% 10% 0 V tPHL Out-of-Phase Output 90% tf VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORM INPUT R
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 25-Sep-2013 Status (1) SNJ54HC20W ACTIVE Package Type Package Pins Package Drawing Qty CFP W 14 1 Eco Plan Lead/Ball Finish (2) TBD MSL Peak Temp Op Temp (°C) Device Marking (3) A42 N / A for Pkg Type (4/5) -55 to 125 8403901DA SNJ54HC20W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74HC20DR SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 6.5 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.0 2.1 8.0 16.0 Q1 SN74HC20DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC20NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC20DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC20DT SOIC D 14 250 367.0 367.0 38.0 SN74HC20NSR SO NS 14 2000 367.0 367.0 38.0 SN74HC20PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74HC20PWT TSSOP PW 14 250 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.