Datasheet

 
  
  
SCLS307B– JANUARY 1996 – REVISED JANUARY 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max I
CC
D Typical t
pd
= 12 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Eight Flip-Flops With Single-Rail Outputs
D Clock Enable Latched to Avoid False
Clocking
D Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
description/ordering information
These devices are positive-edge-triggered octal
D-type flip-flops with an enable input. The ’HC377
devices are similar to the ’HC273 devices, but
feature a latched clock-enable (CLKEN
) input
instead of a common clear.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
Q outputs on the positive-going edge of the clock
(CLK) pulse, if CLKEN
is low. Clock triggering
occurs at a particular voltage level and is not
directly related to the transition time of the
positive-going pulse. When CLK is at either the
high or low level, the D input has no effect at the
output. These devices are designed to prevent
false clocking by transitions at CLKEN
.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N Tube SN74HC377N SN74HC377N
40°Cto85°C
SOIC DW
Tube SN74HC377DW
HC377
–40°C to 85°C SOIC – DW
Tape and reel SN74HC377DWR
HC377
SOP – NS Tape and reel SN74HC377NSR HC377
CDIP – J Tube SNJ54HC377J SNJ54HC377J
–55°C to 125°C
CFP – W Tube SNJ54HC377W SNJ54HC377W
55 C
to
125 C
LCCC – FK Tube SNJ54HC377FK SNJ54HC377FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1D
1Q
CLKEN
5Q
5D
V
8Q
4Q
GND
CLK
SN54HC377 . . . FK PACKAGE
(TOP VIEW)
CC
SN54HC377 ...J OR W PACKAGE
SN74HC377 ...DW, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLKEN
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
        
         
       
   
        
       
        

Summary of content (18 pages)