Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Binary counter 74HC Negative slope 33 MHz TSSOP 16

 

   

SCLS158E − DECEMBER 1982 − REVISED SEPTEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Typical t

= 12 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

SN54HC4020 ...J OR W PACKAGE

SN74HC4020 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

SN54HC4020 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

GND

CLR

CLK

3212019

910111213

CLR

CLK

GND

description/ordering information

The ’HC4020 devices are 14-stage binary ripple-carry counters that advance on the negative-going edge of the

clock pulse. The counters are reset to zero (all outputs low) independently of the clock (CLK) input when the

clear (CLR) input goes high.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC4020N SN74HC4020N

Tube of 40 SN74HC4020D

SOIC − D

Reel of 2500 SN74HC4020DR

HC4020

SOIC − D

Reel of 250 SN74HC4020DT

HC4020

−40°C to 85°C

SOP − NS Reel of 2000 SN74HC4020NSR HC4020

−40 C to 85 C

SSOP − DB Reel of 2000 SN74HC4020DBR HC4020

Tube of 90 SN74HC4020PW

TSSOP − PW

Reel of 2000 SN74HC4020PWR

HC4020

TSSOP − PW

Reel of 250 SN74HC4020PWT

HC4020

CDIP − J Tube of 25 SNJ54HC4020J SNJ54HC4020J

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC4020W SNJ54HC4020W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HC4020FK SNJ54HC4020FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (20 pages)

PAGE 1
SCLS158E − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 12 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 QM QL VCC QK QJ QH QI CLR CLK QA QN QF NC QE QG 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 QJ QH NC QI CLR QD GND NC QA
PAGE 2
SCLS158E − DECEMBER 1982 − REVISED SEPTEMBER 2003 FUNCTION TABLE (each buffer) INPUTS FUNCTION CLK CLR ↑ L No change ↓ L Advance to next stage X H All outputs L logic diagram (positive logic) CLR 11 R CLK 10 R T R R T 6 QG T QH T R T R T T 7 5 4 QA QD QE QF R T 13 R 9 R T R R T 12 R T 14 QI QJ R T 15 QK R T T 1 2 3 QL QM QN Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
PAGE 3
SCLS158E − DECEMBER 1982 − REVISED SEPTEMBER 2003 recommended operating conditions (see Note 3) SN54HC4020 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO Input voltage NOM MAX 2 5 6 NOM MAX 2 5 6 1.5 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition rise/fall time MIN 1.
PAGE 4
SCLS158E − DECEMBER 1982 − REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency CLK high or low tw Pulse duration CLR high tsu Setup time, CLR inactive before CLK↓ TA = 25°C MIN MAX SN54HC4020 MIN MAX SN74HC4020 MIN MAX 2V 5.5 3.7 4.3 4.5 V 28 19 22 6V 33 22 25 2V 90 135 115 4.5 V 18 27 23 6V 15 23 20 2V 70 105 90 4.
PAGE 5
SCLS158E − DECEMBER 1982 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Reference Input 0V CL = 50 pF (see Note A) tsu Data Input LOAD CIRCUIT Input 50% 0V tPLH In-Phase Output 90% 50% 10% 90% tPHL 90% VCC 50% 10% 0 V 90% tr tf VOLTAGE WAVEFORMS SETUP AND INPUT RISE AND FALL TIMES tPHL 90% tr Out-of-Phase Output 50% 10% VCC 50% VCC 50% VOH 50% 10% VOL tf tf 50% 10% 50% 50% 0V
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC4020DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC4020PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC4020PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC4020DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC4020PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC4020PWT TSSOP PW 16 250 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.