Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Binary counter 74HC Negative slope 33 MHz SOIC 16 N

 

   

SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Typical t

= 12 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

SN54HC4040 ...J OR W PACKAGE

SN74HC4040 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

SN54HC4040 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

GND

CLR

CLK

3212019

910111213

CLR

CLK

GND

description/ordering information

The ’HC4040 devices are 12-stage asynchronous binary counters, with the outputs of all stages available

externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low.

The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay

circuits, counter controls, and frequency-dividing circuits.

ORDERING INFORMATION

PACKAGE

†

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC4040N SN74HC4040N

Tube of 40 SN74HC4040D

SOIC − D

Reel of 2500 SN74HC4040DR

HC4040

SOIC − D

Reel of 250 SN74HC4040DT

HC4040

−40°C to 85°C

SOP − NS Reel of 2000 SN74HC4040NSR HC4040

−40 C to 85 C

SSOP − DB Reel of 2000 SN74HC4040DBR HC4040

Tube of 90 SN74HC4040PW

TSSOP − PW

Reel of 2000 SN74HC4040PWR

HC4040

TSSOP − PW

Reel of 250 SN74HC4040PWT

HC4040

CDIP − J Tube of 25 SNJ54HC4040J SNJ54HC4040J

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC4040W SNJ54HC4040W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HC4040FK SNJ54HC4040FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (23 pages)

PAGE 1
SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 12 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max QF QL 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QK QJ QH QI CLR CLK QA QE QG NC QD QC 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 QJ QH NC QI CLR QB GND NC QA CL
PAGE 2
SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003 FUNCTION TABLE (each buffer) INPUTS FUNCTION CLK CLR ↑ L No change ↓ L Advance to next stage X H All outputs L logic diagram (positive logic) CLR 11 R CLK 10 R T R R T T 4 QF QG T R T T 7 6 5 3 QA QB QC QD QE R T 2 R 9 R T R R T 13 QH R T 12 QI R T 14 QJ T 15 QK 1 QL Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
PAGE 3
SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003 recommended operating conditions (see Note 3) SN54HC4040 VCC Supply voltage VIH VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO Input voltage NOM MAX 2 5 6 NOM MAX 2 5 6 1.5 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition rise/fall time MIN 1.
PAGE 4
SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency CLK high or low tw Pulse duration CLR high tsu Setup time, CLR inactive before CLK↓ TA = 25°C MIN MAX SN54HC4040 MIN MAX SN74HC4040 MIN MAX 2V 5.5 3.7 4.3 4.5 V 28 19 22 6V 33 22 25 2V 90 135 115 4.5 V 18 27 23 6V 15 23 20 2V 70 105 90 4.
PAGE 5
SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 50% 10% 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% tPHL Out-of-Phase Output
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 25-Sep-2013 Status (1) SNJ54HC4040W ACTIVE Package Type Package Pins Package Drawing Qty CFP W 16 1 Eco Plan Lead/Ball Finish (2) TBD MSL Peak Temp Op Temp (°C) Device Marking (3) A42 N / A for Pkg Type (4/5) -55 to 125 8500401FA SNJ54HC4040W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC4040DBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74HC4040DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC4040DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC4040DBR SSOP DB 16 2000 367.0 367.0 38.0 SN74HC4040DR SOIC D 16 2500 367.0 367.0 38.0 SN74HC4040DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC4040PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC4040PWT TSSOP PW 16 250 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.