Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Binary counter 74HC Negative slope 33 MHz TSSOP 16

 

     

SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Typical t

= 14 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D Allow Design of Either RC- or

Crystal-Oscillator Circuits

SN54HC4060 ...J OR W PACKAGE

SN74HC4060 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

SN54HC4060 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

GND

CLR

CLKI

CLKO

3212019

910111213

CLR

CLKI

CLKO

GND

CLKO

description/ordering information

The ’HC4060 devices consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator

configuration allows design of either RC- or crystal-oscillator circuits. A high-to-low transition on the clock (CLKI)

input increments the counter. A high level at the clear (CLR) input disables the oscillator (CLKO

goes high and

CLKO goes low) and resets the counter to zero (all Q outputs low).

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC4060N SN74HC4060N

Tube of 40 SN74HC4060D

SOIC − D

Reel of 2500 SN74HC4060DR

HC4060

SOIC − D

Reel of 250 SN74HC4060DT

HC4060

−40°C to 85°C

SOP − NS Reel of 2000 SN74HC4060NSR HC4060

−40 C to 85 C

SSOP − DB Reel of 2000 SN74HC4060DBR HC4060

Tube of 90 SN74HC4060PW

TSSOP − PW

Reel of 2000 SN74HC4060PWR

HC4060

TSSOP − PW

Reel of 250 SN74HC4060PWT

HC4060

CDIP − J Tube of 25 SNJ54HC4060J SNJ54HC4060J

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC4060W SNJ54HC4060W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HC4060FK SNJ54HC4060FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (20 pages)

PAGE 1
SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 14 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Allow Design of Either RC- or Crystal-Oscillator Circuits 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QJ QH QI CLR CLKI CLKO CLKO QN QF NC QE QG 4 3 2 1 20 19 18 5
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SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 FUNCTION TABLE (each buffer) INPUTS FUNCTION CLK CLR ↑ L No change ↓ L Advance to next stage X H All outputs L logic diagram (positive logic) R R T CLR R T R T 4 6 QF QG R T 14 R T 13 QH T R T 15 QI QJ R T T 1 2 3 QL QM QN 12 R R T 9 CLKI R 11 10 R T R T R T T CLKO CLKO Pin numbers shown are for the D, DB, J, N, NS, PW, and W package
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SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 recommended operating conditions (see Note 3) SN54HC4060 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO ∆t/∆v MIN NOM MAX 2 5 6 Input voltage MAX 2 5 6 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition rise/fall time NOM 1.
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SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency CLKI high or low tw Pulse duration CLR high tsu Setup time, CLR inactive before CLKI↓ TA = 25°C MIN MAX SN54HC4060 MIN MAX SN74HC4060 MIN MAX 2V 5.5 3.7 4.3 4.5 V 28 19 22 6V 33 22 25 2V 90 135 115 4.
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SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Reference Input 0V CL = 50 pF (see Note A) tsu Data Input LOAD CIRCUIT Input 50% 0V tPLH In-Phase Output 90% 50% 10% 90% tPHL 90% VCC 50% 10% 0 V 90% tr tf VOLTAGE WAVEFORMS SETUP AND INPUT RISE AND FALL TIMES tPHL 90% tr Out-of-Phase Output 50% 10% VCC 50% VCC 50% VOH 50% 10% VOL tf tf 50
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SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003 CONNECTING AN RC-OSCILLATOR CIRCUIT TO THE ’HC4060 DEVICES The ’HC4060 devices consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC- or crystal-oscillator circuits. When an RC-oscillator circuit is implemented, two resistors and a capacitor are required.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74HC4060DBR SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 12.0 16.0 Q1 DB 16 2000 330.0 16.4 8.2 6.6 2.5 SN74HC4060DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC4060NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC4060DBR SSOP DB 16 2000 367.0 367.0 38.0 SN74HC4060DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC4060NSR SO NS 16 2000 367.0 367.0 38.0 SN74HC4060PWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74HC4060PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC4060PWRG4 TSSOP PW 16 2000 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.