Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state SOIC 20

SN54HC563, SN74HC563

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCLS145C – DECEMBER 1982 – REVISED MARCH 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Wide Operating Voltage Range of 2 V to 6 V

High-Current 3-State Outputs Drive Bus

Lines Directly or Up To 15 LSTTL Loads

Low Power Consumption, 80-µA Max I

Typical t

= 21 ns

±6-mA Output Drive at 5 V

Low Input Current of 1 µA Max

Bus-Structured Pinout

GND

SN54HC563 ...J OR W PACKAGE

SN74HC563 . . . DW OR N PACKAGE

(TOP VIEW)

3212019

910111213

SN54HC563 . . . FK PACKAGE

(TOP VIEW)

7Q 1Q

GND

description/ordering information

These 8-bit transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive

or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports,

bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q

outputs follow the complements of the data (D) inputs. When

LE is taken low, the outputs are latched at the inverses of the levels set up at the D inputs.

A buffered output-enable (OE

) input places the eight outputs in either a normal logic state (high or low logic

levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines

significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines

without interface or pullup components.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

does not affect internal operations of the latches. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – N Tube SN74HC563N SN74HC563N

–40°C to 85°C

SOIC DW

Tube SN74HC563DW

HC563

SOIC

–

Tape and reel SN74HC563DWR

HC563

CDIP – J Tube SNJ54HC563J SNJ54HC563J

–55°C to 125°C

CFP – W Tube SNJ54HC563W SNJ54HC563W

LCCC – FK Tube SNJ54HC563FK SNJ54HC563FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Summary of content (13 pages)

PAGE 1
SN54HC563, SN74HC563 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS145C – DECEMBER 1982 – REVISED MARCH 2003 Typical tpd = 21 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Bus-Structured Pinout SN54HC563 . . . FK PACKAGE (TOP VIEW) 2D 1D SN54HC563 . . . J OR W PACKAGE SN74HC563 . . .
PAGE 2
SN54HC563, SN74HC563 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS145C – DECEMBER 1982 – REVISED MARCH 2003 FUNCTION TABLE (each latch) INPUTS OUTPUT Q OE LE D L H H L L H L H L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 2 19 1Q 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
SN54HC563, SN74HC563 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS145C – DECEMBER 1982 – REVISED MARCH 2003 recommended operating conditions (see Note 3) SN54HC563 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO tt Low-level input voltage NOM MAX 2 5 6 MAX 2 5 6 3.15 3.15 4.2 4.2 0 UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition (rise and fall) time NOM 1.
PAGE 4
SN54HC563, SN74HC563 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS145C – DECEMBER 1982 – REVISED MARCH 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC tw Pulse duration, LE high Setup time, data before LE↓ ↓ tsu Hold time, data after LE↓ ↓ th TA = 25°C MIN MAX SN54HC563 MIN MAX SN74HC563 MIN 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 50 75 63 4.5 V 10 15 13 6V 9 13 11 2V 5 5 5 4.
PAGE 5
SN54HC563, SN74HC563 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS145C – DECEMBER 1982 – REVISED MARCH 2003 switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER SN54HC563 SN74HC563 TO (OUTPUT) VCC 2V 95 200 300 250 D Q 4.5 V 33 40 60 50 6V 29 34 51 43 2V 103 225 335 285 4.
PAGE 6
SN54HC563, SN74HC563 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS145C – DECEMBER 1982 – REVISED MARCH 2003 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test CL (see Note A) PARAMETER S1 Test Point tPZH ten RL 1 kΩ tPZL tPHZ tdis S2 RL 1 kΩ Data Input VCC 50% 10% 50% 50% 0V In-Phase Output 50% 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% tf Closed Closed Open Open Open VCC th 90% 90% VCC 50% 10% 0 V tf 50% 10% Output Control (Low-Level Enablin
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74HC563DWR Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 2.7 12.0 24.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC563DWR SOIC DW 20 2000 367.0 367.0 45.
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