Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state SOIC 20

 

   

  

SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D High-Current 3-State Outputs Drive Bus

Lines Directly or Up To 15 LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Typical t

= 21 ns

D ±6-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D Bus-Structured Pinout

3212019

910111213

GND

SN54HC573A ...FK PACKAGE

(TOP VIEW)

SN54HC573A ...J OR W PACKAGE

SN74HC573A . . . DB, DW, N, OR PW PACKAGE

(TOP VIEW)

GND

description/ordering information

These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive

or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports,

bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the

outputs are latched to retain the data that was set up.

A buffered output-enable (OE

) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC573AN SN74HC573AN

SOIC − DW

Tube of 40 SN74HC573ADW

HC573A

−40°C to 85°C

SOIC − DW

Reel of 2500 SN74HC573ADWR

HC573A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74HC573ADBR HC573A

TSSOP − PW

Reel of 2000 SN74HC573APWR

HC573A

TSSOP − PW

Reel of 250 SN74HC573APWT

HC573A

CDIP − J Tube of 25 SNJ54HC573AJ SNJ54HC573AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC573AW SNJ54HC573AW

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HC573AFK SNJ54HC573AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

    !"#   $"%&! '#(

'"! !  $#!! $# )# #  #* "#

'' +,( '"! $!#- '#  #!#&, !&"'#

#-  && $##(

 $'"! !$&  ./0 && $## # ##'

"&# )#+# #'(  && )# $'"! $'"!

$!#- '#  #!#&, !&"'# #-  && $##(

Summary of content (22 pages)

PAGE 1
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State Outputs Drive Bus D D D D Lines Directly or Up To 15 LSTTL Loads D Low Power Consumption, 80-µA Max ICC SN54HC573A . . . J OR W PACKAGE SN74HC573A . . .
PAGE 2
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does not affect the internal operations of the latches.
PAGE 3
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003 recommended operating conditions (see Note 3) SN54HC573A VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO tt MIN NOM MAX 2 5 6 Input voltage MAX 2 5 6 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition (rise and fall) time NOM 1.
PAGE 4
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC tw Pulse duration, LE high tsu Setup time, data before LE↓ th Hold time, data after LE↓ TA = 25°C MIN MAX SN54HC573A MIN MAX SN74HC573A MIN 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 50 75 63 4.5 V 10 15 13 6V 9 13 11 2V 20 24 24 4.
PAGE 5
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER SN54HC573A SN74HC573A TO (OUTPUT) VCC 2V 95 200 300 250 D Q 4.5 V 33 40 60 50 6V 21 34 51 43 2V 103 225 335 285 4.
PAGE 6
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER S1 Test Point From Output Under Test ten RL tPZH RL CL 50 pF or 150 pF 1 kΩ tPZL tdis S2 tPLZ 1 kΩ 50 pF −− 50 pF or 150 pF tpd or tt LOAD CIRCUIT 50% Closed Closed Open Open Closed Closed Open Open Open 50% 0V 50% tsu 0V tw Data 50% Input 10% VCC Low-Level Pulse 50% 50% 50% 0V tPLH 50% 10% tPHL 90% 90% tr
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74HC573ADBR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74HC573ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74HC573APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC573ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74HC573ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74HC573APWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74HC573APWT TSSOP PW 20 250 367.0 367.0 38.
PAGE 13
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 19
PAGE 20
PAGE 21
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 22
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.