Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Standard Three-state, Non-inverting TSSOP 20

SN54HC574, SN74HC574

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCLS148F − DECEMBER 1982 − REVISED AUGUST 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D High-Current 3-State Noninverting Outputs

Drive Bus Lines Directly or Up To 15 LSTTL

Loads

D Low Power Consumption, 80-μA Max I

D Typical t

= 22 ns

D ±6-mA Output Drive at 5 V

D Low Input Current of 1 μA Max

D Bus-Structured Pinout

description/ordering information

These octal edge-triggered D-type flip-flops

feature 3-state outputs designed specifically for

bus driving. They are particularly suitable for

implementing buffer registers, I/O ports,

bidirectional bus drivers, and working registers.

The eight flip-flops enter data on the low-to-high

transition of the clock (CLK) input.

A buffered output-enable (OE

) input can be used

to place the eight outputs in either a normal logic

state (high or low logic levels) or the

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines without interface or pullup components.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 20 SN74HC574N SN74HC574N

SOIC DW

Tube of 25 SN74HC574DW

HC574

SOIC − DW

Reel of 2000 SN74HC574DWR

HC574

40°Cto85°C

SSOP − DB Reel of 2000 SN74HC574DBR HC574

−40°C to 85°C

SOP − NS Reel of 2000 SN74HC574NSR HC574

Tube of 70 SN74HC574PW

TSSOP − PW

Reel of 2000 SN74HC574PWR

HC574

TSSOP

Reel of 250 SN74HC574PWT

HC574

CDIP − J Tube of 20 SNJ54HC574J SNJ54HC574J

−55°C to 125°C

CFP − W Tube of 85 SNJ54HC574W SNJ54HC574W

LCCC − FK Tube of 55 SNJ54HC574FK SNJ54HC574FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

3212019

910111213

GND

CLK

SN54HC574 . . . FK PACKAGE

(TOP VIEW)

SN54HC574 ...J OR W PACKAGE

SN74HC574 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

GND

CLK

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (22 pages)

PAGE 1
SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F − DECEMBER 1982 − REVISED AUGUST 2003 D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State Noninverting Outputs Drive Bus Lines Directly or Up To 15 LSTTL Loads Low Power Consumption, 80-μA Max ICC Typical tpd = 22 ns ±6-mA Output Drive at 5 V Low Input Current of 1 μA Max Bus-Structured Pinout OE 1D 2D 3D 4D 5D 6D 7D 8D GND description/ordering information These octal edge-triggered D-type flip-flops
PAGE 2
SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F − DECEMBER 1982 − REVISED AUGUST 2003 description/ordering information (continued) OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
PAGE 3
SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F − DECEMBER 1982 − REVISED AUGUST 2003 recommended operating conditions (see Note 3) SN54HC574 VCC Supply voltage VCC = 2 V VIH VCC = 4.5 V High-level High level input voltage VCC = 6 V MIN NOM MAX 2 5 6 Input voltage VO Output voltage TA 5 6 3.15 4.2 0 0 Input transition rise/fall time 2 4.2 VCC = 2 V Δt/Δv MAX 3.15 VCC = 6 V VI NOM 1.5 VCC = 4.
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SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F − DECEMBER 1982 − REVISED AUGUST 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C VCC fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time, data before CLK↑ th Hold time,, data after CLK↑ MIN SN54HC574 MAX MIN MAX SN74HC574 MIN MAX 2V 6 4 5 4.5 V 30 20 24 6V 38 24 28 2V 80 120 100 4.
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SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F − DECEMBER 1982 − REVISED AUGUST 2003 switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd ten tt CLK OE Any Q Any Q Any yQ VCC TA = 25°C MIN TYP SN54HC574 MAX MIN MAX SN74HC574 MIN 2V 6 5 4.5 V 30 24 6V 36 28 MAX UNIT MHz 2V 105 265 400 330 4.
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SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F − DECEMBER 1982 − REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test CL (see Note A) PARAMETER S1 Test Point tPZH ten RL RL 1 kΩ tPZL tPHZ tdis tPLZ S2 1 kΩ Data Input VCC 50% 10% 50% VCC 0V In-Phase Output 50% 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% Output Control (Low-Level Enabling) tf Closed Closed Open Open Open th 90% 90% VCC 50% 10% 0 V tf
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC574DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74HC574DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74HC574NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC574DBR SN74HC574DWR SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 366.0 364.0 50.0 SN74HC574NSR SO NS 20 2000 367.0 367.0 45.0 SN74HC574PWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74HC574PWRG4 TSSOP PW 20 2000 367.0 367.0 38.0 SN74HC574PWT TSSOP PW 20 250 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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