Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Shift register Push pull PDIP 16

 

  

  

SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D High-Current Outputs Can Drive Up To

15 LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Typical t

= 15 ns

D ±6-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D 8-Bit Serial-In, Parallel-Out Shift Registers

With Storage

D Independent Direct Overriding Clears on

Shift and Storage Registers

D Independent Clocks for Both Shift and

Storage Registers

SN54HC594 ...J OR W PACKAGE

SN74HC594 . . . D, DW, OR N PACKAGE

(TOP VIEW)

SN54HC594 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

GND

SER

RCLR

RCLK

SRCLK

SRCLR

H′

3212019

91011 1213

SER

RCLR

RCLK

SRCLK

SRCLR

GND

′

description/ordering information

The ’HC594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage

, SRCLR) inputs are provided on both the shift and

storage registers. A serial (Q

H′

) output is provided for cascading purposes.

Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks

are connected together, the shift register always is one count pulse ahead of the storage register.

The parallel (Q

−Q

) outputs have high-current capability. Q

H′

is a standard output.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HC594N SN74HC594N

Tube of 40 SN74HC594D

−40°C to 85°C

SOIC − D

Reel of 2500 SN74HC594DR

HC594

−40°C to 85°C

SOIC − D

Reel of 250 SN74HC594DT

HC594

SOIC − DW

Tube of 40 SN74HC594DW

HC594

SOIC − DW

Reel of 2000 SN74HC594DWR

HC594

CDIP − J Tube of 25 SNJ54HC594J SNJ54HC594J

−55°C to 125°C

CFP − W Tube of 150 SNJ54HC594W SNJ54HC594W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HC594FK SNJ54HC594FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

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)%(%"##(,

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (18 pages)

PAGE 1
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003 D Wide Operating Voltage Range of 2 V to 6 V D High-Current Outputs Can Drive Up To D Low Input Current of 1 µA Max D 8-Bit Serial-In, Parallel-Out Shift Registers 15 LSTTL Loads With Storage D Low Power Consumption, 80-µA Max ICC D Typical tpd = 15 ns D ±6-mA Output Drive at 5 V SN54HC594 . . . J OR W PACKAGE SN74HC594 . . .
PAGE 2
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003 FUNCTION TABLE INPUTS 2 FUNCTION SER SRCLK SRCLR RCLK RCLR X X L X X Shift register is cleared. L ↑ H X X First stage of shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of shift register goes high. Other stages store the data of previous stage, respectively. L ↓ H X X Shift register state is not changed.
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SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003 logic diagram (positive logic) RCLR RCLK SRCLR SRCLK SER 13 12 10 11 14 1D C1 R R 3R C3 3S 2S 2R C2 R R 3R C3 3S 2S 2R C2 R R 3R C3 3S 2S 2R C2 R R 3R C3 3S 2S 2R C2 R R 3R C3 3S 2S 2R C2 R R 3R C3 3S 2S 2R C2 R R 3R C3 3S 2S 2R C2 R R 3R C3 3S 15 1 2 3 4 5 6 7 9 Pin numbers shown are for the D, DW, J, N, and W packages.
PAGE 4
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003 timing diagram SRCLK SER RCLK SRCLR RCLR QA QB QC QD QE QF QG QH QH′ absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . .
PAGE 5
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003 recommended operating conditions (see Note 3) SN54HC594 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO Input voltage NOM MAX 2 5 6 NOM MAX 2 5 6 1.5 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition (rise and fall) time MIN 1.
PAGE 6
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency SRCLK or RCLK high or low tw Pulse duration SRCLR or RCLR low SER before SRCLK↑ SRCLK↑ before RCLK↑† tsu Setup time SRCLR low before RCLK↑ SRCLR high (inactive) before SRCLK↑ RCLR high (inactive) before SRCLK↑ th Hold time, SER after SRCLK SRCLK↑ TA = 25°C MIN
PAGE 7
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax SRCLK QH H′ tpd RCLK QA−QH SRCLR QH H′ tPHL RCLR QA−QH QH H′ tt QA−QH VCC MIN TA = 25°C TYP MAX SN54HC594 MIN MAX SN74HC594 MIN 2V 5 8 3.3 4 4.
PAGE 8
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% 50% 10% tPHL Out-of-Phase Output
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC594DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC594DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 SN74HC594DWRG4 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC594DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC594DWR SOIC DW 16 2000 366.0 364.0 50.0 SN74HC594DWRG4 SOIC DW 16 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.