Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Receiver, transceiver PDIP 20

 

  

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SCLS303D − JANUARY 1996 − REVISED AUGUST 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Wide Operating Voltage Range of 2 V to 6 V

D High-Current 3-State Outputs Can Drive Up

To 15 LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Typical t

= 8 ns

D ±6-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D Inverting Logic

SN54HC640 ...J OR W PACKAGE

SN74HC640 ...DW, N, NS, OR PW PACKAGE

(TOP VIEW)

SN54HC640 . . . FK PACKAGE

(TOP VIEW)

DIR

GND

3212019

10 11 12 13

DIR

GND

description/ordering information

These octal bus transceivers are designed for asynchronous two-way communication between data buses.

These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending upon the

level at the direction-control (DIR) input. The output-enable (OE

) input can be used to disable the device so the

buses are effectively isolated.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 20 SN74HC640N SN74HC640N

SOIC − DW

Tube of 25 SN74HC640DW

HC640

SOIC − DW

Reel of 2000 SN74HC640DWR

HC640

−40°C to 85°C

SOP − NS Reel of 2000 SN74HC640NSR HC640

−40 C to 85 C

Tube of 70 SN74HC640PW

TSSOP − PW

Reel of 2000 SN74HC640PWR

HC640

TSSOP − PW

Reel of 250 SN74HC640PWT

HC640

CDIP − J Tube of 20 SNJ54HC640J SNJ54HC640J

−55°C to 125°C

CFP − W Tube of 85 SNJ54HC640W SNJ54HC640W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HC640FK SNJ54HC640FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (19 pages)

PAGE 1
SCLS303D − JANUARY 1996 − REVISED AUGUST 2003 D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State Outputs Can Drive Up D D D D To 15 LSTTL Loads D Low Power Consumption, 80-µA Max ICC Typical tpd = 8 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inverting Logic 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 A2 A1 DIR VCC VCC OE B1 B2 B3 B4 B5 B6 B7 B8 A3 A4 A5 A6 A7 4 3 2 1 20 19 18 5
PAGE 2
SCLS303D − JANUARY 1996 − REVISED AUGUST 2003 FUNCTION TABLE (each transceiver) INPUTS OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation logic diagram (positive logic) OE DIR A1 19 1 2 18 B1 To Seven Other Transceivers absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
SCLS303D − JANUARY 1996 − REVISED AUGUST 2003 recommended operating conditions (see Note 3) SN54HC640 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO ∆t/∆v MIN NOM MAX 2 5 6 Input voltage MAX 2 5 6 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition rise/fall time NOM 1.5 0 Output voltage MIN 1.
PAGE 4
SCLS303D − JANUARY 1996 − REVISED AUGUST 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) TA = 25°C TYP MAX SN54HC640 SN74HC640 PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V 29 105 160 130 tpd A or B B or A 4.5 V 10 21 32 26 6V 8 18 27 22 ten OE tdis OE tt A or B A or B A or B MIN MIN MAX MIN MAX 2V 109 230 340 290 4.
PAGE 5
SCLS303D − JANUARY 1996 − REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER Test Point From Output Under Test tPZH S1 ten RL CL (see Note A) 1 kΩ tPZL tPHZ tdis S2 RL tPLZ tpd or tt 1 kΩ −− LOAD CIRCUIT CL S1 S2 50 pF or 150 pF Open Closed Closed Open Open Closed Closed Open Open Open 50 pF 50 pF or 150 pF VCC Input 50% 50% 0V tPLH In-Phase Output 50% 10% tPHL 90% VOH 50% 10% V OL tf 90% tr
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74HC640DWR Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DW 20 2000 330.0 24.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.8 13.0 2.7 12.0 24.0 Q1 SN74HC640NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1 SN74HC640PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC640DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74HC640NSR SO NS 20 2000 367.0 367.0 45.0 SN74HC640PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74HC640PWT TSSOP PW 20 250 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.