Datasheet

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SN74HC74-Q1

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP

WITH CLEAR AND PRESET

SCLS577A − MARCH 2004 − REVISED APRIL 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Qualified for Automotive Applications

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Typical t

= 15 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

description/ordering information

The SN74HC74 device contains two independent D-type positive-edge-triggered flip-flops. A low level at the

preset (PRE

) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When

PRE

and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred

to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and

is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed

without affecting the levels at the outputs.

ORDERING INFORMATION

{

PACKAGE

‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

40°C to 125°C

SOIC − D Reel of 2500 SN74HC74QDRQ1 HC74Q

−40°C to 125°C

TSSOP − PW Reel of 2000 SN74HC74QPWRQ1 HC74Q

†

For the most current package and ordering information, see the Package Option Addendum at the end of

this document, or see the TI web site at http://www.ti.com.

‡

Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.

FUNCTION TABLE

INPUTS OUTPUTS

PRE CLR CLK D Q Q

L H X X H L

H LXXLH

L LXXH

†

H H ↑ HHL

H H ↑ LLH

H H L X Q

†

This configuration is nonstable; that is, it does not

persist when PRE

or CLR returns to its inactive

(high) level.

1CLR

1CLK

1PRE

GND

2CLR

2CLK

2PRE

D OR PW PACKAGE

(TOP VIEW)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (13 pages)

PAGE 1
SN74HC74-Q1 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCLS577A − MARCH 2004 − REVISED APRIL 2008 D D D D D D D Qualified for Automotive Applications Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 15 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max D OR PW PACKAGE (TOP VIEW) 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q descri
PAGE 2
SN74HC74-Q1 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCLS577A − MARCH 2004 − REVISED APRIL 2008 logic diagram (positive logic) PRE CLK C C Q TG C C C C C D TG TG TG Q C C C CLR absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 3
SN74HC74-Q1 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCLS577A − MARCH 2004 − REVISED APRIL 2008 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 20 µA VOH VI = VIH or VIL IOH = −4 mA IOH = −5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II VI = VCC or 0 ICC VI = VCC or 0, TA = 25°C VCC IO = 0 MIN TYP MAX 2V 1.9 1.998 1.9 4.5 V 4.4 4.499 4.4 6V 5.
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SN74HC74-Q1 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCLS577A − MARCH 2004 − REVISED APRIL 2008 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax PRE or CLR Q or Q tpd CLK Q or Q tt Q or Q VCC TA = 25°C MIN TYP MAX MIN 2V 6 10 4.2 4.5 V 31 50 21 6V 36 60 25 MAX UNIT MHz 2V 70 230 345 4.
PAGE 5
SN74HC74-Q1 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCLS577A − MARCH 2004 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point VCC High-Level Pulse 50% 50% 0V CL = 50 pF (see Note A) tw VCC Low-Level Pulse LOAD CIRCUIT 50% 50% 0V VOLTAGE WAVEFORMS PULSE DURATIONS VCC VCC Reference Input 50% Input 50% 50% 0V 0V tsu Data Input 50% 10% 90% tr th tPLH 90% VCC 50% 10% 0 V In-Phase Output 90% 90% tr tf VOLTAGE WAVEFORM
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC74QPWRG4Q1 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC74QPWRQ1 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC74QPWRG4Q1 TSSOP PW 14 2000 367.0 367.0 35.0 SN74HC74QPWRQ1 TSSOP PW 14 2000 367.0 367.0 35.
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